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# /space/home/slher/rel/Beken/v6_4_5/macsw/ip/lmac/src/hal/hal_desc.h

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    00001
    00015 #ifndef _HAL_DESC_H_
    00016 #define _HAL_DESC_H_
    00017
    00027 /*
    00028  * INCLUDE FILES
    00029  ****************************************************************************************
    00030  */
    00031 #include "co_int.h"
    00032 // for mac_addr
    00033 #include "mac.h"
    00034 // for mac frame definitions
    00035 #include "mac_frame.h"
    00036 // for dma_desc
    00037 #include "dma.h"
    00038 // for CO_BIT
    00039 #include "co_math.h"
    00040 // for co_list_hdr
    00041 #include "co_list.h"
    00042 // for phy_channel_info
    00043 #include "phy.h"
    00044 // for DBG info format
    00045 #include "dbg.h"
    00046 #if (NX_RADAR_DETECT || NX_UF_EN)
    00047 // for hal_dma_desc
    00048 #include "hal_dma.h"
    00049 #endif //(NX_RADAR_DETECT)
    00050
    00051 /*
    00052  * DEFINES
    00053  ****************************************************************************************
    00054  */
    00056 #define RADAR_PULSE_MAX   4
    00058 #define RADAR_EVENT_MAX   10
    00060 #define UNSUP_RX_VECT_MAX   8
    00061
    00063 #define TX_HEADER_DESC_PATTERN 0xCAFEBABE
    00065 #define TX_PAYLOAD_DESC_PATTERN 0xCAFEFADE
    00067 #define RX_HEADER_DESC_PATTERN 0xBAADF00D
    00069 #define RX_PAYLOAD_DESC_PATTERN 0xC0DEDBAD
    00070
    00071 #if NX_MON_DATA
    00072 #define RX_MACHDR_BACKUP_LEN    64
    00073 #endif
    00074
    00075 //----------------------------------------------------------------------------------------
    00076 // TBD: BUF CONTROL INFO definitions
    00077 //----------------------------------------------------------------------------------------
    00079 #define TBD_DONE_HW             CO_BIT(31)
    00081 #define TBD_INTERRUPT_EN        CO_BIT(0)
    00082
    00083 //----------------------------------------------------------------------------------------
    00084 // THD: PHY CONTROL INFO definitions
    00085 //----------------------------------------------------------------------------------------
    00086 #if !NX_MAC_HE
    00088 #define SOUNDING_TX_BIT         CO_BIT(0)
    00090 #define SMOOTHING_TX_BIT        CO_BIT(1)
    00092 #define SMOOTHING_PROT_TX_BIT   CO_BIT(2)
    00093 #endif
    00095 #define USE_BW_SIG_TX_BIT       CO_BIT(3)
    00097 #define DYN_BW_TX_BIT           CO_BIT(4)
    00099 #define DOZE_ALLOWED_TX_BIT     CO_BIT(5)
    00101 #define CONT_TX_BIT             CO_BIT(6)
    00103 #define USER_POS_OFT            12
    00105 #define USER_POS_MASK           (0x3 << USER_POS_OFT)
    00107 #define USE_RIFS_TX_BIT         CO_BIT(14)
    00109 #define USE_MUMIMO_TX_BIT       CO_BIT(15)
    00111 #define GID_TX_OFT              16
    00113 #define GID_TX_MASK             (0x3F << GID_TX_OFT)
    00115 #define PAID_TX_OFT             22
    00117 #define PAID_TX_MASK            (0x1FF << PAID_TX_OFT)
    00118
    00119 //----------------------------------------------------------------------------------------
    00120 // THD: MAC CONTROL INFO 1 definitions
    00121 //----------------------------------------------------------------------------------------
    00123 #define PROT_FRM_DURATION_OFT             16
    00125 #define PROT_FRM_DURATION_MSK             (0xFFFF << PROT_FRM_DURATION_OFT)
    00126
    00128 #define WRITE_ACK                         CO_BIT(14)
    00130 #define LOW_RATE_RETRY                    CO_BIT(13)
    00132 #define LSTP_PROT                         CO_BIT(12)
    00134 #define LSTP                              CO_BIT(11)
    00135
    00136 // Expected Acknowledgment
    00138 #define EXPECTED_ACK_OFT                  9
    00140 #define EXPECTED_ACK_MSK                  (0x3 << EXPECTED_ACK_OFT)
    00142 #define EXPECTED_ACK_NO_ACK               (0x0 << EXPECTED_ACK_OFT)
    00144 #define EXPECTED_ACK_NORMAL_ACK           (0x1 << EXPECTED_ACK_OFT)
    00146 #define EXPECTED_ACK_BLOCK_ACK            (0x2 << EXPECTED_ACK_OFT)
    00148 #define EXPECTED_ACK_COMPRESSED_BLOCK_ACK (0x3 << EXPECTED_ACK_OFT)
    00149
    00150 //----------------------------------------------------------------------------------------
    00151 // THD MACCTRLINFO2 fields
    00152 //----------------------------------------------------------------------------------------
    00154 #define TS_VALID_BIT                      CO_BIT(0)
    00155
    00157 #define FRM_TYPE_OFT                      1
    00159 #define FRM_TYPE_MSK                      (0x3<<FRM_TYPE_OFT)
    00160
    00162 #define FRM_TYPE_MNG                      (0<<FRM_TYPE_OFT)
    00164 #define FRM_TYPE_CNTL                     (1<<FRM_TYPE_OFT)
    00166 #define FRM_TYPE_DATA                     (2<<FRM_TYPE_OFT)
    00167
    00169 #define FRM_SUBTYPE_OFT                   3
    00171 #define FRM_SUBTYPE_MSK                   (0xF<<FRM_SUBTYPE_OFT)
    00172
    00174 #define FRM_CNTL_SUBTYPE_BAR              (8<<FRM_SUBTYPE_OFT)
    00176 #define FRM_CNTL_SUBTYPE_BA               (9<<FRM_SUBTYPE_OFT)
    00177
    00179 #define INTERRUPT_EN_TX                   CO_BIT(8)
    00180
    00182 #define NB_BLANK_DELIM_OFT                9
    00184 #define NB_BLANK_DELIM_MSK                (0x3FF << NB_BLANK_DELIM_OFT)
    00185
    00188 #define WHICHDESC_OFT                     19
    00190 #define WHICHDESC_MSK                     (0x07 << WHICHDESC_OFT)
    00192 #define WHICHDESC_UNFRAGMENTED_MSDU       (0x00 << WHICHDESC_OFT)
    00194 #define WHICHDESC_FRAGMENTED_MSDU_FIRST   (0x01 << WHICHDESC_OFT)
    00196 #define WHICHDESC_FRAGMENTED_MSDU_INT     (0x02 << WHICHDESC_OFT)
    00198 #define WHICHDESC_FRAGMENTED_MSDU_LAST    (0x03 << WHICHDESC_OFT)
    00200 #define WHICHDESC_AMPDU_EXTRA             (0x04 << WHICHDESC_OFT)
    00202 #define WHICHDESC_AMPDU_FIRST             (0x05 << WHICHDESC_OFT)
    00204 #define WHICHDESC_AMPDU_INT               (0x06 << WHICHDESC_OFT)
    00206 #define WHICHDESC_AMPDU_LAST              (0x07 << WHICHDESC_OFT)
    00207
    00209 #define AMPDU_OFT                         21
    00211 #define AMPDU_BIT                         CO_BIT(AMPDU_OFT)
    00212
    00214 #define UNDER_BA_SETUP_BIT                CO_BIT(22)
    00215
    00217 #define DONT_TOUCH_DUR                    CO_BIT(28)
    00218
    00219
    00220 //----------------------------------------------------------------------------------------
    00221 //THD STATINFO fields
    00222 //----------------------------------------------------------------------------------------
    00224 #define NUM_RTS_RETRIES_OFT                0
    00226 #define NUM_RTS_RETRIES_MSK               (0xFF << NUM_RTS_RETRIES_OFT)
    00228 #define NUM_MPDU_RETRIES_OFT               8
    00230 #define NUM_MPDU_RETRIES_MSK              (0xFF << NUM_MPDU_RETRIES_OFT)
    00232 #define RETRY_LIMIT_REACHED_BIT            CO_BIT(16)
    00234 #define LIFETIME_EXPIRED_BIT               CO_BIT(17)
    00236 #define BA_FRAME_RECEIVED_BIT              CO_BIT(18)
    00238 #define HE_TB_TX_BIT                       CO_BIT(22)
    00240 #define FRAME_SUCCESSFUL_TX_BIT            CO_BIT(23)
    00242 #define A_MPDU_LAST                        (0x0F << 26)
    00244 #define BW_TX_OFT                          24
    00246 #define BW_TX_MSK                          (0x3 << BW_TX_OFT)
    00248 #define BW_20MHZ_TX                        (0x0 << BW_TX_OFT)
    00250 #define BW_40MHZ_TX                        (0x1 << BW_TX_OFT)
    00252 #define BW_80MHZ_TX                        (0x2 << BW_TX_OFT)
    00254 #define BW_160MHZ_TX                       (0x3 << BW_TX_OFT)
    00256 #define DESC_DONE_TX_BIT                   CO_BIT(31)
    00258 #define DESC_DONE_SW_TX_BIT                CO_BIT(30)
    00259
    00262
    00264 #define RATE_CONTROL_STEPS      4
    00265
    00267 #define POLICY_TABLE_PATTERN    0xBADCAB1E
    00268
    00269 // Policy Table: PHY Control 1 Information field
    00270 #if NX_MAC_HE
    00272 #define SOUNDING_TX_OFT         0
    00274 #define SOUNDING_TX_BIT         CO_BIT(SOUNDING_TX_OFT)
    00276 #define SMOOTHING_TX_OFT        1
    00278 #define SMOOTHING_TX_BIT        CO_BIT(SMOOTHING_TX_OFT)
    00280 #define SMOOTHING_PROT_TX_OFT   2
    00282 #define SMOOTHING_PROT_TX_BIT   CO_BIT(SMOOTHING_PROT_TX_OFT)
    00283 #endif
    00285 #define BF_FORM_EXT_PT_OFT      3
    00287 #define BF_FORM_EXT_PT_MASK     (0x1 << BF_FORM_EXT_PT_OFT)
    00289 #define NO_EXTN_SS_PT_OFT       4
    00291 #define NO_EXTN_SS_PT_MASK      (0x3 << NO_EXTN_SS_PT_OFT)
    00293 #define FEC_CODING_PT_OFT       6
    00295 #define FEC_CODING_PT_BIT       CO_BIT(FEC_CODING_PT_OFT)
    00297 #define STBC_PT_OFT             7
    00299 #define STBC_PT_MASK            (0x3 << STBC_PT_OFT)
    00301 #define NX_TX_PT_OFT            14
    00303 #define NX_TX_PT_MASK           (0x7 << NX_TX_PT_OFT)
    00305 #define NX_TX_PROT_PT_OFT       17
    00307 #define NX_TX_PROT_PT_MASK      (0x7 << NX_TX_PROT_PT_OFT)
    00309 #define DOPPLER_OFT             20
    00311 #define DOPPLER_BIT             CO_BIT(DOPPLER_OFT)
    00313 #define SPATIAL_REUSE_OFT       24
    00315 #define SPATIAL_REUSE_MASK      (0xF << SPATIAL_REUSE_OFT)
    00316
    00317 // Policy Table: PHY Control 2 Information field
    00319 #define ANTENNA_SET_PT_OFT      0
    00321 #define ANTENNA_SET_PT_MASK     0XFF
    00323 #define SMM_INDEX_PT_OFT        8
    00325 #define SMM_INDEX_PT_MASK       (0XFF << SMM_INDEX_PT_OFT)
    00327 #define BMFED_OFT               16
    00329 #define BMFED_BIT               CO_BIT(BMFED_OFT)
    00331 #define BMCHANGE_OFT            17
    00333 #define BMCHANGE_BIT            CO_BIT(BMCHANGE_OFT)
    00335 #define UPLINK_FLAG_OFT         18
    00337 #define UPLINK_FLAG_BIT         CO_BIT(UPLINK_FLAG_OFT)
    00339 #define BSS_COLOR_OFT           20
    00341 #define BSS_COLOR_MASK         (0X3F << BSS_COLOR_OFT)
    00343 #define PKT_EXTENSION_OFT       26
    00345 #define PKT_EXTENSION_MASK     (0X07 << PKT_EXTENSION_OFT)
    00346
    00347 // Policy Table: MAC Control 1 Information field
    00349 #define KEYSRAM_INDEX_OFT       0
    00351 #define KEYSRAM_INDEX_MASK      (0X3FF << KEYSRAM_INDEX_OFT)
    00353 #define KEYSRAM_INDEX_RA_OFT    10
    00355 #define KEYSRAM_INDEX_RA_MASK   (0X3FF << KEYSRAM_INDEX_RA_OFT)
    00356
    00357 // Policy Table: MAC Control 2 Information field.
    00359 #define LONG_RETRY_LIMIT_OFT    0
    00361 #define LONG_RETRY_LIMIT_MASK   (0XFF << LONG_RETRY_LIMIT_OFT)
    00363 #define SHORT_RETRY_LIMIT_OFT   8
    00365 #define SHORT_RETRY_LIMIT_MASK  (0XFF << SHORT_RETRY_LIMIT_OFT)
    00367 #define RTS_THRSHOLD_OFT        16 // Bits 16-23
    00369 #define RTS_THRSHOLD_MASK       (0XFF << RTS_THRSHOLD_OFT)
    00370
    00371 // Policy Table: Rate Control Information field
    00373 #define MCS_INDEX_TX_RCX_OFT    0
    00375 #define MCS_INDEX_TX_RCX_MASK   (0X7F << MCS_INDEX_TX_RCX_OFT)
    00377 #define BW_TX_RCX_OFT           7
    00379 #define BW_TX_RCX_MASK          (0X3 << BW_TX_RCX_OFT)
    00381 #define SHORT_GI_TX_RCX_OFT     9
    00383 #define SHORT_GI_TX_RCX_MASK    (0x1 << SHORT_GI_TX_RCX_OFT)
    00385 #define PRE_TYPE_TX_RCX_OFT     10
    00387 #define PRE_TYPE_TX_RCX_MASK    (0x1 << PRE_TYPE_TX_RCX_OFT)
    00389 #define HE_GI_TYPE_TX_RCX_OFT   9
    00391 #define HE_GI_TYPE_TX_RCX_MASK  (0x3 << HE_GI_TYPE_TX_RCX_OFT)
    00393 #define GI_TYPE_0_8             (0x0 << HE_GI_TYPE_TX_RCX_OFT)
    00395 #define GI_TYPE_1_6             (0x1 << HE_GI_TYPE_TX_RCX_OFT)
    00397 #define GI_TYPE_3_2             (0x2 << HE_GI_TYPE_TX_RCX_OFT)
    00399 #define FORMAT_MOD_TX_RCX_OFT   11
    00401 #define FORMAT_MOD_TX_RCX_MASK  (0X7 << FORMAT_MOD_TX_RCX_OFT)
    00403 #define PROT_FRM_EX_RCX_OFT     14
    00405 #define PROT_FRM_EX_RCX_MASK    (0X7 << PROT_FRM_EX_RCX_OFT)
    00407 #define PROT_NO_PROT            (0x0 << PROT_FRM_EX_RCX_OFT)
    00409 #define PROT_SELF_CTS           (0x1 << PROT_FRM_EX_RCX_OFT)
    00411 #define PROT_RTS_CTS            (0x2 << PROT_FRM_EX_RCX_OFT)
    00413 #define PROT_RTS_CTS_WITH_QAP   (0x3 << PROT_FRM_EX_RCX_OFT)
    00415 #define PROT_STBC               (0x4 << PROT_FRM_EX_RCX_OFT)
    00416
    00418 #define MCS_INDEX_PROT_TX_RCX_OFT  17
    00420 #define MCS_INDEX_PROT_TX_RCX_MASK (0x7F << MCS_INDEX_PROT_TX_RCX_OFT)
    00422 #define BW_PROT_TX_RCX_OFT      24
    00424 #define BW_PROT_TX_RCX_MASK     (0x3 << BW_PROT_TX_RCX_OFT)
    00426 #define FORMAT_MOD_PROT_TX_RCX_OFT  26
    00428 #define FORMAT_MOD_PROT_TX_RCX_MASK (0x7 << FORMAT_MOD_PROT_TX_RCX_OFT)
    00430 #define N_RETRY_RCX_OFT         29
    00432 #define N_RETRY_RCX_MASK        (0x7 << N_RETRY_RCX_OFT)
    00433
    00434 // Values of the FORMAT_MOD fields
    00436 #define FORMATMOD_NON_HT          0
    00438 #define FORMATMOD_NON_HT_DUP_OFDM 1
    00440 #define FORMATMOD_HT_MF           2
    00442 #define FORMATMOD_HT_GF           3
    00444 #define FORMATMOD_VHT             4
    00446 #define FORMATMOD_HE_SU           5
    00450 #define FORMATMOD_HE_MU           6
    00452 #define FORMATMOD_HE_ER           7
    00453
    00455 #define BW_20MHZ                  0
    00457 #define BW_40MHZ                  1
    00459 #define BW_80MHZ                  2
    00461 #define BW_160MHZ                 3
    00462
    00463 // VHT specific NSS and MCS values
    00465 #define VHT_NSS_OFT               4
    00467 #define VHT_NSS_MASK              (0x7 << VHT_NSS_OFT)
    00469 #define VHT_MCS_OFT               0
    00471 #define VHT_MCS_MASK              (0xF << VHT_MCS_OFT)
    00472
    00473 // HT specific NSS and MCS values (valid only for MCS <= 31)
    00475 #define HT_NSS_OFT               3
    00477 #define HT_NSS_MASK              (0x3 << HT_NSS_OFT)
    00479 #define HT_MCS_OFT               0
    00481 #define HT_MCS_MASK              (0x7 << HT_MCS_OFT)
    00482
    00483 // Policy Table: Power Control Information field
    00485 #define TX_PWR_LEVEL_PT_RCX_OFT         0
    00487 #define TX_PWR_LEVEL_PT_RCX_MASK        (0xff << TX_PWR_LEVEL_PT_RCX_OFT)
    00489 #define TX_PWR_LEVEL_PROT_PT_RCX_OFT    8
    00491 #define TX_PWR_LEVEL_PROT_PT_RCX_MASK   (0xff << TX_PWR_LEVEL_PROT_PT_RCX_OFT)
    00493 #define TX_PWR_LEVEL_MASK               (TX_PWR_LEVEL_PT_RCX_MASK | TX_PWR_LEVEL_PROT_PT_RCX_MASK)
    00495 #define TX_PWR_LEVEL_SET(pwr)           (((pwr) << TX_PWR_LEVEL_PROT_PT_RCX_OFT) |       \
    00496                                          ((pwr) << TX_PWR_LEVEL_PT_RCX_OFT))
    00498 #define TX_HE_LTF_TYPE_PT_RCX_OFT       16
    00500 #define TX_HE_LTF_TYPE_PT_RCX_MASK      (0x03 << TX_HE_LTF_TYPE_PT_RCX_OFT)
    00502 #define TX_1x_HE_LTF_FOR_3_2_US         (0x00 << TX_HE_LTF_TYPE_PT_RCX_OFT)
    00504 #define TX_2x_HE_LTF_FOR_6_4_US         (0x01 << TX_HE_LTF_TYPE_PT_RCX_OFT)
    00506 #define TX_4x_HE_LTF_FOR_12_8_US        (0x02 << TX_HE_LTF_TYPE_PT_RCX_OFT)
    00508 #define TX_HE_DCM_OFT                   18
    00510 #define TX_HE_DCM_BIT                   CO_BIT(TX_HE_DCM_OFT)
    00512
    00515
    00516 // Compressed Policy Table: Secondary User Information field
    00518 #define MCS_IDX_TX_CPT_OFT      0
    00520 #define MCS_IDX_TX_CPT_MASK     (0x7F << MCS_IDX_TX_CPT_OFT)
    00522 #define FEC_CODING_CPT_OFT      7
    00524 #define FEC_CODING_CPT_BIT      CO_BIT(FEC_CODING_CPT_OFT)
    00526 #define SMM_INDEX_CPT_OFT       8
    00528 #define SMM_INDEX_CPT_MASK      (0XFF << SMM_INDEX_CPT_OFT)
    00530 #define KEYSRAM_INDEX_CPT_OFT   16
    00532 #define KEYSRAM_INDEX_CPT_MASK  (0X3FF << KEYSRAM_INDEX_OFT)
    00533
    00535
    00538
    00540 #define KEY_IDX_OFT                       15
    00542 #define KEY_IDX_MSK                       (0x3FF << KEY_IDX_OFT)
    00544 #define KEY_IDX_VALID_BIT                 CO_BIT(25)
    00546 #define IMM_RSP_AC_OFT                    11
    00548 #define IMM_RSP_AC_MSK                    (0x03 << IMM_RSP_AC_OFT)
    00549
    00551 #define RX_PD_LASTBUF 0x0001
    00553 #define RX_PD_DONE 0x0002
    00554
    00556 #define RX_HD_KEYIDV 0x02000000
    00558 #define RX_HD_KEYID 0x01FF8000
    00560 #define RX_HD_KEYID_LSB 15
    00562 #define RX_HD_DONE 0x00004000
    00564 #define RX_HD_SUCCESS 0x00002000
    00566 #define RX_HD_GA_FRAME 0x00000400
    00568 #define RX_HD_ADDRMIS 0x00000200
    00570 #define RX_HD_FCSERR 0x0100
    00571 #if NX_RX_RING
    00573 #define RX_HD_UNDEF_ERR 0x00000080
    00575 #define RX_HD_DECR_ERR 0x00000040
    00577 #define RX_HD_DECRTYPE_MSK 0x0000003C
    00579 #define RX_HD_DECRTYPE_OFT 2
    00581 #define RX_HD_DECR_UNENC (0x00 << RX_HD_DECRTYPE_OFT)
    00583 #define RX_HD_DECR_WEP (0x01 << RX_HD_DECRTYPE_OFT)
    00585 #define RX_HD_DECR_TKIP (0x02 << RX_HD_DECRTYPE_OFT)
    00587 #define RX_HD_DECR_CCMP128 (0x03 << RX_HD_DECRTYPE_OFT)
    00589 #define RX_HD_DECR_CCMP256 (0x04 << RX_HD_DECRTYPE_OFT)
    00591 #define RX_HD_DECR_GCMP128 (0x05 << RX_HD_DECRTYPE_OFT)
    00593 #define RX_HD_DECR_GCMP256 (0x06 << RX_HD_DECRTYPE_OFT)
    00595 #define RX_HD_DECR_WAPI (0x07 << RX_HD_DECRTYPE_OFT)
    00597 #define RX_HD_DECR_UNK (0x0F << RX_HD_DECRTYPE_OFT)
    00599 #define RX_HD_DECRSTATUS (RX_HD_DECR_ERR | RX_HD_DECRTYPE_MSK)
    00601 #define RX_HD_DECR_WEP_SUCCESS (RX_HD_DECR_WEP)
    00603 #define RX_HD_DECR_TKIP_SUCCESS (RX_HD_DECR_TKIP)
    00605 #define RX_HD_DECR_CCMP128_SUCCESS (RX_HD_DECR_CCMP128)
    00607 #define RX_HD_DECR_CCMP256_SUCCESS (RX_HD_DECR_CCMP256)
    00609 #define RX_HD_DECR_GCMP128_SUCCESS (RX_HD_DECR_GCMP128)
    00611 #define RX_HD_DECR_GCMP256_SUCCESS (RX_HD_DECR_GCMP256)
    00613 #define RX_HD_DECR_WAPI_SUCCESS (RX_HD_DECR_WAPI)
    00614 #else
    00616 #define RX_HD_PHY_ERR 0x00000080
    00618 #define RX_HD_UNDEF_ERR 0x00000040
    00620 #define RX_HD_DECRSTATUS 0x0000001C
    00622 #define RX_HD_DECR_UNENC 0x0000
    00624 #define RX_HD_DECR_WEP_SUCCESS 0x0014
    00626 #define RX_HD_DECR_TKIP_SUCCESS 0x0018
    00628 #define RX_HD_DECR_CCMP128_SUCCESS 0x001C
    00629 #endif
    00631 #define RX_HD_RSP_FRM 0x00000002
    00633 #define RX_HD_RXVEC2V 0x00000001
    00636 #define RX_HD_KEYID_GET(__s) (((__s) & RX_HD_KEYID) >> RX_HD_KEYID_LSB)
    00639 #define RX_HD_DONE_GET(__s) ((__s) & RX_HD_DONE)
    00642 #define RX_HD_SUCCESS_GET(__s) ((__s) & (RX_HD_SUCCESS | RX_HD_FCSERR))
    00643
    00645
    00647 #define RXL_HWDESC_RXV_LEN    40
    00648
    00649
    00650
    00653
    00655 #define RXVEC1_NUM_REG      4
    00656
    00657 #if (NX_MAC_VER >= 20)
    00660 #define RXVEC_FORMATMOD(__x)   (((__x) & 0x0000000F))
    00663 #define RXVEC_PRETYPE(__x)     (((__x) & 0x00000080) >> 7)
    00666 #define RXVEC_LEGRATE(__x)     (((__x) & 0x000000F0) >> 4)
    00669 #ifdef CFG_RWTL
    00670 #define RXVEC_RSSI1(__x)       ((int32_t)((__x) & 0x0000FF00) >> 8)
    00671 #else
    00672 #define RXVEC_RSSI1(__x)       (((__x) & 0x0000FF00) >> 8)
    00673 #endif
    00676 #define RXVEC_HTLENGTH_0(__x)    (((__x) & 0x0000FFFF))
    00677 #else
    00680 #define RXVEC_LEGRATE(__x)     (((__x) & 0x0000F000) >> 12)
    00683 #define RXVEC_HTLENGTH_0(__x)    (((__x) & 0xFFFF0000) >> 16)
    00686 #define RXVEC_HTLENGTH_1(__x)    (((__x) & 0x0000000F))
    00689 #define RXVEC_PRETYPE(__x)     (((__x) & 0x00008000) >> 15)
    00692 #define RXVEC_FORMATMOD(__x)   (((__x) & 0x00070000) >> 16)
    00695 #ifdef CFG_RWTL
    00696 #define RXVEC_RSSI1(__x)       ((int32_t)((__x) & 0xFF000000) >> 24)
    00697 #else
    00698 #define RXVEC_RSSI1(__x)       (((__x) & 0xFF000000) >> 24)
    00699 #endif
    00702 #ifdef CFG_RWTL
    00703 #define RXVEC_RSSI2(__x)       ((int32_t)(((__x) & 0x000000FF) << 24) >> 24)
    00704 #else
    00705 #define RXVEC_RSSI2(__x)       (((__x) & 0x000000FF))
    00706 #endif
    00707 #endif // (NX_MAC_VER >= 20)
    00708
    00710
    00715 #define RX_AMPDU_AMPDUCNT(__x)   (((__x) & 0xC000) >> 14)
    00718 #define RX_AMPDU_MPDUCNT(__x)    ((__x) & 0x3F00)
    00720
    00721
    00723 enum
    00724 {
    00726     HW_RATE_1MBPS = 0,
    00728     HW_RATE_2MBPS,
    00730     HW_RATE_5_5MBPS,
    00732     HW_RATE_11MBPS,
    00734     HW_RATE_6MBPS,
    00736     HW_RATE_9MBPS,
    00738     HW_RATE_12MBPS,
    00740     HW_RATE_18MBPS,
    00742     HW_RATE_24MBPS,
    00744     HW_RATE_36MBPS,
    00746     HW_RATE_48MBPS,
    00748     HW_RATE_54MBPS
    00749 };
    00750
    00752 struct machdr
    00753 {
    00755     uint16_t reserved;
    00757     uint16_t framectrl;
    00759     uint16_t duration;
    00761     struct mac_addr macaddr1;
    00763     struct mac_addr macaddr2;
    00765     struct mac_addr macaddr3;
    00767     uint16_t seq_ctrl;
    00769     struct mac_addr macaddr4;
    00771     uint16_t qos_ctrl;
    00773     uint16_t carriedfr_ctrl;
    00775     uint32_t ht_ctrl;
    00777     uint32_t iv;
    00779     uint32_t ext_iv;
    00780 };
    00781
    00784 struct tx_policy_tbl
    00785 {
    00787     uint32_t upatterntx;
    00789     uint32_t phycntrlinfo1;
    00791     uint32_t phycntrlinfo2;
    00793     uint32_t maccntrlinfo1;
    00795     uint32_t maccntrlinfo2;
    00797     uint32_t ratecntrlinfo[RATE_CONTROL_STEPS];
    00799     uint32_t powercntrlinfo[RATE_CONTROL_STEPS];
    00800 };
    00801
    00804 struct tx_compressed_policy_tbl
    00805 {
    00807     uint32_t upatterntx;
    00809     uint32_t sec_user_control;
    00810 };
    00811
    00813 struct tx_hd
    00814 {
    00816     uint32_t             upatterntx;
    00818     uint32_t             nextfrmexseq_ptr;
    00820     uint32_t             nextmpdudesc_ptr;
    00822     union {
    00824         uint32_t             first_pbd_ptr;
    00826         uint32_t             sec_user1_ptr;
    00827     };
    00829     union {
    00831         uint32_t             datastartptr;
    00833         uint32_t             sec_user2_ptr;
    00834     };
    00836     union {
    00838         uint32_t             dataendptr;
    00840         uint32_t             sec_user3_ptr;
    00841     };
    00843     uint32_t             frmlen;
    00845     uint32_t             frmlifetime;
    00847     uint32_t             phyctrlinfo;
    00849     uint32_t             policyentryaddr;
    00851     uint32_t             optlen[3];
    00853     uint32_t             macctrlinfo1;
    00855     uint32_t             macctrlinfo2;
    00857     uint32_t             statinfo;
    00859     uint32_t             mediumtimeused;
    00860 };
    00861
    00863 struct tx_pbd
    00864 {
    00866     uint32_t             upatterntx;
    00868     uint32_t             next;
    00870     uint32_t             datastartptr;
    00872     uint32_t             dataendptr;
    00874     uint32_t             bufctrlinfo;
    00875 };
    00876
    00878 struct tx_dmadesc
    00879 {
    00881     struct tx_hd header;
    00883     struct tx_pbd buffer;
    00885     struct machdr macheader;
    00886 };
    00887
    00889 struct rx_vector_1
    00890 {
    00892     uint32_t            recvec1a;
    00894     uint32_t            recvec1b;
    00896     uint32_t            recvec1c;
    00898     uint32_t            recvec1d;
    00899 };
    00900
    00902 struct rx_vector_2
    00903 {
    00905     uint32_t            recvec2a;
    00907     uint32_t            recvec2b;
    00908 };
    00909
    00911 struct rx_hd
    00912 {
    00914     uint32_t            upatternrx;
    00916     uint32_t            next;
    00918     uint32_t            first_pbd_ptr;
    00920     struct rxdesc      *rxdesc;
    00922     uint32_t            datastartptr;
    00924     uint32_t            dataendptr;
    00927     uint32_t            headerctrlinfo;
    00929     uint16_t            frmlen;
    00931     uint16_t            ampdu_stat_info;
    00933     uint32_t            tsflo;
    00935     uint32_t            tsfhi;
    00937     struct rx_vector_1  rx_vec_1;
    00939     struct rx_vector_2  rx_vec_2;
    00941     uint32_t            statinfo;
    00942 };
    00943
    00945 struct rx_pbd
    00946 {
    00948     uint32_t            upattern;
    00951     uint32_t            next;
    00953     uint32_t            datastartptr;
    00955     uint32_t            dataendptr;
    00957     uint16_t            bufstatinfo;
    00959     uint16_t            reserved;
    00960 };
    00961
    00962 #if NX_MON_DATA
    00964 struct rxu_machdrdesc
    00965 {
    00967     uint32_t buf_len;
    00969     uint32_t buffer[RX_MACHDR_BACKUP_LEN / 4];
    00970 };
    00971 #endif
    00972
    00974 struct rx_dmadesc
    00975 {
    00977     struct rx_hd hd;
    00979     struct phy_channel_info phy_info;
    00980     #if NX_UMAC_PRESENT
    00982     uint32_t flags;
    00983     #if NX_AMSDU_DEAGG
    00985     uint32_t amsdu_hostids[NX_MAX_MSDU_PER_RX_AMSDU - 1];
    00986     #endif
    00987     #if NX_MON_DATA
    00989     struct rxu_machdrdesc mac_hdr_backup;
    00990     #endif
    00991     #endif
    00993     uint32_t pattern;
    00995     struct dma_desc dma_desc;
    00996 };
    00997
    00999 struct rx_payloaddesc
    01000 {
    01002     struct rx_pbd pbd;
    01004     struct dma_desc dma_desc[NX_DMADESC_PER_RX_PDB_CNT];
    01005     #if !NX_RX_RING
    01007     uint32_t buffer[NX_RX_PAYLOAD_LEN/4];
    01008     #endif
    01009 };
    01010
    01012 struct tx_cfm_tag
    01013 {
    01014     #if NX_UMAC_PRESENT
    01015     #if !NX_FULLY_HOSTED
    01017     uint16_t pn[4];
    01019     uint16_t sn;
    01021     uint16_t timestamp;
    01022     #endif
    01024     int8_t credits;
    01027     uint8_t ampdu_size;
    01028     #if NX_AMSDU_TX
    01030     uint16_t amsdu_size;
    01031     #endif
    01032     #endif
    01033
    01035     uint32_t status;
    01036 };
    01037
    01039 struct tx_hw_desc
    01040 {
    01041     #if !NX_FULLY_HOSTED
    01043     struct tx_cfm_tag cfm;
    01045     struct dma_desc dma_desc;
    01046     #endif
    01048     struct tx_hd    thd;
    01049 };
    01050
    01051 #if NX_RADAR_DETECT
    01053 struct radar_pulse_array_desc
    01054 {
    01056     struct phy_radar_pulse pulse[RADAR_PULSE_MAX];
    01058     uint32_t idx;
    01060     uint32_t cnt;
    01061 };
    01062
    01064 struct radar_event_desc
    01065 {
    01067     struct co_list_hdr list_hdr;
    01069     struct dma_desc dma_desc;
    01071     struct hal_dma_desc_tag gp_dma_desc;
    01073     struct radar_pulse_array_desc pulse_array;
    01074 };
    01075 #endif
    01076
    01077 #if NX_UF_EN
    01079 struct rx_vector_desc
    01080 {
    01082     struct phy_channel_info phy_info;
    01083
    01085     struct rx_vector_1 rx_vec_1;
    01086     #if !NX_FULLY_HOSTED
    01088     uint32_t pattern;
    01089     #endif // !NX_FULLY_HOSTED
    01090 };
    01091
    01093 struct unsup_rx_vector_desc
    01094 {
    01096     struct co_list_hdr list_hdr;
    01097     #if !NX_FULLY_HOSTED
    01099     struct dma_desc dma_desc;
    01101     struct hal_dma_desc_tag gp_dma_desc;
    01103     #endif // !NX_FULLY_HOSTED
    01104     struct rx_vector_desc rx_vector;
    01105 };
    01106 #endif
    01107
    01109 struct debug_info_tag
    01110 {
    01112     volatile struct dma_desc dma_desc;
    01114     struct dbg_debug_info_tag dbg_info;
    01115 };
    01116
    01117 /*
    01118  * GLOBAL VARIABLES
    01119  ****************************************************************************************
    01120  */
    01121 #if NX_RADAR_DETECT
    01122 extern struct radar_event_desc radar_event_desc_array[RADAR_EVENT_MAX];
    01123 #endif
    01124
    01125 #if NX_UF_EN
    01126 extern struct unsup_rx_vector_desc rx_vector_desc_array[UNSUP_RX_VECT_MAX];
    01127 #endif
    01128
    01129 #if NX_BCN_AUTONOMOUS_TX
    01131 extern struct dma_desc bcn_dwnld_desc;
    01132 #endif
    01133
    01135 extern struct tx_hw_desc       tx_hw_desc0[RW_USER_MAX * NX_TXDESC_CNT0];
    01137 extern struct tx_hw_desc       tx_hw_desc1[RW_USER_MAX * NX_TXDESC_CNT1];
    01139 extern struct tx_hw_desc       tx_hw_desc2[RW_USER_MAX * NX_TXDESC_CNT2];
    01141 extern struct tx_hw_desc       tx_hw_desc3[RW_USER_MAX * NX_TXDESC_CNT3];
    01142 #if (NX_BEACONING)
    01144 extern struct tx_hw_desc       tx_hw_desc4[NX_TXDESC_CNT4];
    01145 #endif
    01146
    01147 #if NX_DEBUG_DUMP
    01149 extern struct debug_info_tag   debug_info;
    01150 #endif
    01151
    01162 __INLINE int8_t hal_desc_get_rssi(struct rx_vector_1 *rx_vec_1, int8_t *rx_rssi)
    01163 {
    01164         int8_t rssi;
    01165
    01166         #if (NX_MAC_VER >= 20)
    01167         rx_rssi[0] = RXVEC_RSSI1(rx_vec_1->recvec1b);
    01168         rx_rssi[1] = RXVEC_RSSI1(rx_vec_1->recvec1b);
    01169         #else
    01170         rx_rssi[0] = RXVEC_RSSI1(rx_vec_1->recvec1c);
    01171         rx_rssi[1] = RXVEC_RSSI2(rx_vec_1->recvec1d);
    01172         #endif // (NX_MAC_VER >= 20)
    01173
    01174         // Set the RSSI value
    01175         if (phy_get_nrx() == 1)
    01176         {
    01177            rssi = (rx_rssi[0] + rx_rssi[1])/2;
    01178         }
    01179         else
    01180         {
    01181            rssi = rx_rssi[0];
    01182         }
    01183
    01184         return rssi;
    01185 }
    01186
    01196 __INLINE uint16_t hal_desc_get_ht_length(struct rx_vector_1 *rx_vec_1)
    01197 {
    01198     uint16_t length;
    01199
    01200     #if (NX_MAC_VER >= 20)
    01201     length = RXVEC_HTLENGTH_0(rx_vec_1->recvec1c);
    01202     #else
    01203     length = RXVEC_HTLENGTH_0(rx_vec_1->recvec1a);
    01204     #endif // (NX_MAC_VER >= 20)
    01205
    01206     return length;
    01207 }
    01208
    01218 __INLINE uint8_t hal_desc_get_rx_format(struct rx_vector_1 *rx_vec_1)
    01219 {
    01220     uint8_t format;
    01221
    01222     #if (NX_MAC_VER >= 20)
    01223     format = RXVEC_FORMATMOD(rx_vec_1->recvec1a);
    01224     #else
    01225     format = RXVEC_FORMATMOD(rx_vec_1->recvec1b);
    01226     #endif // (NX_MAC_VER >= 20)
    01227
    01228     return format;
    01229 }
    01230
    01240 __INLINE uint8_t hal_desc_get_preamble_type(struct rx_vector_1 *rx_vec_1)
    01241 {
    01242     uint8_t pretype;
    01243
    01244     #if (NX_MAC_VER >= 20)
    01245     pretype = RXVEC_PRETYPE(rx_vec_1->recvec1a);
    01246     #else
    01247     pretype = RXVEC_PRETYPE(rx_vec_1->recvec1b);
    01248     #endif // (NX_MAC_VER >= 20)
    01249
    01250     return pretype;
    01251 }
    01252
    01262 __INLINE uint8_t hal_desc_get_legacy_rate(struct rx_vector_1 *rx_vec_1)
    01263 {
    01264     uint8_t rate;
    01265
    01266     #if (NX_MAC_VER >= 20)
    01267     rate = RXVEC_LEGRATE(rx_vec_1->recvec1b);
    01268     #else
    01269     rate = RXVEC_LEGRATE(rx_vec_1->recvec1a);
    01270     #endif // (NX_MAC_VER >= 20)
    01271
    01272     return rate;
    01273 }
    01275
    01276 #endif // _HWIF_DESC_H_