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# /space/home/slher/rel/Beken/v6_4_5/macsw/ip/lmac/src/hal/hal_machw_mib.h

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    00001
    00013 #ifndef _HAL_MIB_H_
    00014 #define _HAL_MIB_H_
    00015
    00025 /*
    00026  * INCLUDE FILES
    00027  ****************************************************************************************
    00028  */
    00029 #include "co_int.h"
    00030
    00031 /*
    00032  * DEFINES
    00033  ****************************************************************************************
    00034  */
    00036 struct machw_mib_tag
    00037 {
    00039     uint32_t dot11_wep_excluded_count;
    00041     uint32_t dot11_fcs_error_count;
    00046     uint32_t nx_rx_phy_error_count;
    00048     uint32_t nx_rd_fifo_overflow_count;
    00053     uint32_t nx_tx_underun_count;
    00055     uint32_t reserved_1[7];
    00057     uint32_t nx_qos_utransmitted_mpdu_count[8];
    00059     uint32_t nx_qos_gtransmitted_mpdu_count[8];
    00064     uint32_t dot11_qos_failed_count[8];
    00069     uint32_t dot11_qos_retry_count[8];
    00071     uint32_t dot11_qos_rts_success_count[8];
    00073     uint32_t dot11_qos_rts_failure_count[8];
    00075     uint32_t nx_qos_ack_failure_count[8];
    00077     uint32_t nx_qos_ureceived_mpdu_count[8];
    00079     uint32_t nx_qos_greceived_mpdu_count[8];
    00084     uint32_t nx_qos_ureceived_other_mpdu[8];
    00086     uint32_t dot11_qos_retries_received_count[8];
    00091     uint32_t nx_utransmitted_amsdu_count[8];
    00096     uint32_t nx_gtransmitted_amsdu_count[8];
    00098     uint32_t dot11_failed_amsdu_count[8];
    00100     uint32_t dot11_retry_amsdu_count[8];
    00105     uint32_t dot11_transmitted_octets_in_amsdu[8];
    00110     uint32_t dot11_amsdu_ack_failure_count[8];
    00112     uint32_t nx_ureceived_amsdu_count[8];
    00114     uint32_t nx_greceived_amsdu_count[8];
    00119     uint32_t nx_ureceived_other_amsdu[8];
    00121     uint32_t dot11_received_octets_in_amsdu_count[8];
    00123     uint32_t reserved_2[24];
    00125     uint32_t dot11_transmitted_ampdu_count;
    00127     uint32_t dot11_transmitted_mpdus_in_ampdu_count ;
    00129     uint32_t dot11_transmitted_octets_in_ampdu_count ;
    00131     uint32_t wnlu_ampdu_received_count;
    00133     uint32_t nx_gampdu_received_count;
    00138     uint32_t nx_other_ampdu_received_count ;
    00140     uint32_t dot11_mpdu_in_received_ampdu_count;
    00142     uint32_t dot11_received_octets_in_ampdu_count;
    00144     uint32_t dot11_ampdu_delimiter_crc_error_count;
    00149     uint32_t dot11_implicit_bar_failure_count;
    00154     uint32_t dot11_explicit_bar_failure_count;
    00156     uint32_t reserved_3[5];
    00158     uint32_t dot11_20mhz_frame_transmitted_count;
    00160     uint32_t dot11_40mhz_frame_transmitted_count;
    00162     uint32_t dot11_20mhz_frame_received_count;
    00164     uint32_t dot11_40mhz_frame_received_count;
    00166     uint32_t nx_failed_40mhz_txop;
    00168     uint32_t nx_successful_txops;
    00170     uint32_t reserved_4[4];
    00172     uint32_t dot11_dualcts_success_count;
    00177     uint32_t dot11_stbc_cts_success_count;
    00182     uint32_t dot11_stbc_cts_failure_count;
    00187     uint32_t dot11_non_stbc_cts_success_count;
    00192     uint32_t dot11_non_stbc_cts_failure_count;
    00193
    00194 };
    00195
    00196
    00198
    00199
    00200 #endif //_HAL_MIB_H_