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# /space/home/slher/rel/Beken/v6_4_5/macsw/plf/refip/src/driver/ipc/ipc_shared.h

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    00001
    00013 #ifndef _IPC_SHARED_H_
    00014 #define _IPC_SHARED_H_
    00015
    00094 /*
    00095  * INCLUDE FILES
    00096  ****************************************************************************************
    00097  */
    00098 #ifndef __KERNEL__
    00099 #include "co_int.h"
    00100 #include "tx_swdesc.h"
    00101 #else
    00102 #include "dbg_assert.h"
    00103 #include "lmac_mac.h"
    00104 #endif
    00105
    00106 /*
    00107  * DEFINES AND MACROS
    00108  ****************************************************************************************
    00109  */
    00111 #define IPC_TXQUEUE_CNT     NX_TXQ_CNT
    00112
    00114 #define IPC_RXBUF_CNT       128
    00115
    00116 #if (NX_UMAC_PRESENT)
    00118 #define IPC_RXDESC_CNT      128
    00119 #endif //(NX_UMAC_PRESENT)
    00120
    00122 #define IPC_RADARBUF_CNT       16
    00123
    00125 #define IPC_UNSUPRXVECBUF_CNT   8
    00126
    00128 #define IPC_RXBUF_SIZE 4096
    00129
    00131 #if NX_UMAC_PRESENT
    00132 #define IPC_MSGE2A_BUF_CNT       64
    00133 #else
    00134 #define IPC_MSGE2A_BUF_CNT       4
    00135 #endif
    00136
    00138 #define IPC_DBGBUF_CNT       32
    00139
    00141 #ifdef CFG_RWTL
    00142 #define IPC_A2E_MSG_BUF_SIZE    127 // size in 4-byte words
    00143 #else
    00144 #define IPC_A2E_MSG_BUF_SIZE    127 // size in 4-byte words
    00145 #endif
    00146
    00148 #if NX_UMAC_PRESENT
    00149 #define IPC_E2A_MSG_SIZE_BASE   256 // size in 4-byte words
    00150 #else
    00151 #define IPC_E2A_MSG_SIZE_BASE   15 // size in 4-byte words
    00152 #endif
    00153
    00155 #ifdef CFG_RWTL
    00156 #define IPC_E2A_MSG_PARAM_SIZE   (IPC_E2A_MSG_SIZE_BASE + (IPC_E2A_MSG_SIZE_BASE / 2))
    00157 #else
    00158 #define IPC_E2A_MSG_PARAM_SIZE   IPC_E2A_MSG_SIZE_BASE
    00159 #endif
    00160
    00162 #define IPC_DBG_PARAM_SIZE       256
    00163
    00166 #define RX_DMA_OVER_PATTERN 0xAAAAAA00
    00167
    00172 #define IPC_MSGE2A_VALID_PATTERN 0xADDEDE2A
    00173
    00178 #define IPC_DBG_VALID_PATTERN 0x000CACA0
    00179
    00181 #define DMA_HDR_PHYVECT_LEN    36
    00182
    00184 #define MSG_API_VER     17
    00185
    00189 struct ipc_header
    00190 {
    00192     uint16_t type;
    00194     uint16_t size;
    00195 };
    00196
    00198 struct ipc_msg_elt
    00199 {
    00201     struct ipc_header header __ALIGN4;
    00202 };
    00203
    00205 struct ipc_e2a_msg
    00206 {
    00207     uint16_t id;
    00208     uint16_t dummy_dest_id;
    00209     uint16_t dummy_src_id;
    00210     uint16_t param_len;
    00211     uint32_t param[IPC_E2A_MSG_PARAM_SIZE];
    00212     uint32_t pattern;
    00213 };
    00214
    00216 struct ipc_dbg_msg
    00217 {
    00218     uint32_t string[IPC_DBG_PARAM_SIZE/4];
    00219     uint32_t pattern;
    00220 };
    00221
    00224 struct ipc_a2e_msg
    00225 {
    00226     uint32_t dummy_word;
    00227     uint32_t msg[IPC_A2E_MSG_BUF_SIZE];
    00228 };
    00229
    00230 #if (NX_UMAC_PRESENT)
    00232 struct ipc_shared_rx_buf
    00233 {
    00235     uint32_t hostid;
    00237     uint32_t dma_addr;
    00238 };
    00239
    00241 struct ipc_shared_rx_desc
    00242 {
    00244     uint32_t dma_addr;
    00245 };
    00246 #endif //(NX_UMAC_PRESENT)
    00247
    00248 /*
    00249  * TYPE and STRUCT DEFINITIONS
    00250  ****************************************************************************************
    00251  */
    00252
    00254 struct compatibility_tag {
    00256     uint16_t ipc_shared_size;
    00258     uint16_t msg_api;
    00260     uint8_t ipc_shared_version;
    00262     uint8_t msge2a_buf_cnt;
    00264     uint8_t dbgbuf_cnt;
    00266     uint8_t radarbuf_cnt;
    00268     uint8_t unsuprxvecbuf_cnt;
    00270     uint8_t rxdesc_cnt;
    00272     uint8_t rxbuf_cnt;
    00274     uint8_t bk_txq;
    00276     uint8_t be_txq;
    00278     uint8_t vi_txq;
    00280     uint8_t vo_txq;
    00282     uint8_t bcn_txq;
    00283 };
    00284
    00285 // Indexes are defined in the MIB shared structure
    00287 struct ipc_shared_env_tag
    00288 {
    00290     volatile struct compatibility_tag comp_info;
    00291
    00293     volatile struct ipc_a2e_msg msg_a2e_buf;
    00294
    00296     volatile struct    ipc_e2a_msg msg_e2a_buf;
    00298     volatile struct    dma_desc msg_dma_desc;
    00300     volatile uint32_t  msg_e2a_hostbuf_addr [IPC_MSGE2A_BUF_CNT];
    00301
    00303     volatile struct    ipc_dbg_msg dbg_buf;
    00305     volatile struct    dma_desc dbg_dma_desc;
    00307     volatile uint32_t  dbg_hostbuf_addr [IPC_DBGBUF_CNT];
    00308
    00310     volatile uint32_t  la_dbginfo_addr;
    00311
    00313     volatile uint32_t  pattern_addr;
    00314
    00316     volatile uint32_t  radarbuf_hostbuf [IPC_RADARBUF_CNT]; // buffers @ for Radar Events
    00317
    00319     volatile uint32_t unsuprxvecbuf_hostbuf [IPC_UNSUPRXVECBUF_CNT];
    00320
    00322     volatile struct txdesc_host txdesc0[RW_USER_MAX][NX_TXDESC_CNT0];
    00324     volatile struct txdesc_host txdesc1[RW_USER_MAX][NX_TXDESC_CNT1];
    00326     volatile struct txdesc_host txdesc2[RW_USER_MAX][NX_TXDESC_CNT2];
    00328     volatile struct txdesc_host txdesc3[RW_USER_MAX][NX_TXDESC_CNT3];
    00329     #if (NX_BEACONING)
    00331     volatile struct txdesc_host txdesc4[1][NX_TXDESC_CNT4];
    00332     #endif
    00333
    00334     #if (NX_UMAC_PRESENT)
    00336     volatile struct ipc_shared_rx_desc host_rxdesc[IPC_RXDESC_CNT];
    00338     volatile struct ipc_shared_rx_buf  host_rxbuf[IPC_RXBUF_CNT];
    00339     #else
    00341     volatile uint32_t host_rxbuf[IPC_RXBUF_CNT];
    00342     #endif //(NX_UMAC_PRESENT)
    00343
    00345     volatile uint32_t buffered[NX_REMOTE_STA_MAX][TID_MAX];
    00347     volatile uint16_t trace_pattern;
    00349     volatile uint32_t trace_start;
    00351     volatile uint32_t trace_end;
    00353     volatile uint32_t trace_size;
    00355     volatile uint32_t trace_offset;
    00357     volatile uint32_t trace_nb_compo;
    00359     volatile uint32_t trace_offset_compo;
    00360 };
    00361
    00363 extern struct ipc_shared_env_tag ipc_shared_env;
    00364
    00365 /*
    00366  * TYPE and STRUCT DEFINITIONS
    00367  ****************************************************************************************
    00368  */
    00369
    00372
    00374 #if RW_MUMIMO_TX_EN
    00375 #ifdef CFG_IPC_VER_V10
    00376 #error "MU-MIMO cannot be compiled for old IPC"
    00377 #endif
    00379 #if RW_USER_MAX > 3
    00380 #define IPC_IRQ_A2E_USER_MSK       0xF
    00381 #elif RW_USER_MAX > 2
    00382 #define IPC_IRQ_A2E_USER_MSK       0x7
    00383 #else
    00384 #define IPC_IRQ_A2E_USER_MSK       0x3
    00385 #endif
    00386
    00388 #define IPC_IRQ_A2E_AC0_OFT        8
    00390 #define IPC_IRQ_A2E_AC0_MSK       (IPC_IRQ_A2E_USER_MSK << IPC_IRQ_A2E_AC0_OFT)
    00392 #define IPC_IRQ_A2E_AC1_OFT       (IPC_IRQ_A2E_AC0_OFT + RW_USER_MAX)
    00394 #define IPC_IRQ_A2E_AC1_MSK       (IPC_IRQ_A2E_USER_MSK << IPC_IRQ_A2E_AC1_OFT)
    00396 #define IPC_IRQ_A2E_AC2_OFT       (IPC_IRQ_A2E_AC1_OFT + RW_USER_MAX)
    00398 #define IPC_IRQ_A2E_AC2_MSK       (IPC_IRQ_A2E_USER_MSK << IPC_IRQ_A2E_AC2_OFT)
    00400 #define IPC_IRQ_A2E_AC3_OFT       (IPC_IRQ_A2E_AC2_OFT + RW_USER_MAX)
    00402 #define IPC_IRQ_A2E_AC3_MSK       (IPC_IRQ_A2E_USER_MSK << IPC_IRQ_A2E_AC3_OFT)
    00404 #define IPC_IRQ_A2E_BCN_OFT       (IPC_IRQ_A2E_AC3_OFT + RW_USER_MAX)
    00406 #define IPC_IRQ_A2E_BCN_MSK       CO_BIT(IPC_IRQ_A2E_BCN_OFT)
    00407
    00408 #define IPC_IRQ_A2E_AC_TXDESC     (IPC_IRQ_A2E_AC0_MSK | IPC_IRQ_A2E_AC1_MSK | \
    00409                                    IPC_IRQ_A2E_AC2_MSK | IPC_IRQ_A2E_AC3_MSK)
    00410
    00412 #if !NX_BEACONING || (NX_BCN_AUTONOMOUS_TX && !NX_UMAC_PRESENT)
    00413 #define IPC_IRQ_A2E_BCN_TXDESC      0
    00414 #else
    00415 #define IPC_IRQ_A2E_BCN_TXDESC      (0x01 << IPC_IRQ_A2E_BCN_OFT)
    00416 #endif
    00417
    00419 #define IPC_IRQ_A2E_TXDESC          (IPC_IRQ_A2E_AC_TXDESC | IPC_IRQ_A2E_BCN_TXDESC)
    00420
    00421 #else /* !RW_MUMIMO_TX_EN */
    00422
    00424 #if !NX_BEACONING || (NX_BCN_AUTONOMOUS_TX && !NX_UMAC_PRESENT)
    00425 #define IPC_IRQ_A2E_TXDESC          0x0F00
    00426 #else
    00427 #define IPC_IRQ_A2E_TXDESC          0x1F00
    00428 #endif
    00429
    00430 #endif /* RW_MUMIMO_TX_EN */
    00431
    00433 #define IPC_IRQ_A2E_TXDESC_FIRSTBIT (8)
    00435 #define IPC_IRQ_A2E_RXBUF_BACK      CO_BIT(5)
    00437 #define IPC_IRQ_A2E_RXDESC_BACK     CO_BIT(4)
    00439 #define IPC_IRQ_A2E_MSG             CO_BIT(1)
    00441 #define IPC_IRQ_A2E_DBG             CO_BIT(0)
    00443 #define IPC_IRQ_A2E_ALL             (IPC_IRQ_A2E_TXDESC|IPC_IRQ_A2E_MSG|IPC_IRQ_A2E_DBG)
    00444
    00446
    00449
    00451 #define IPC_IRQ_E2A_TXCFM_POS   7
    00452
    00453 #if RW_MUMIMO_TX_EN
    00454 #ifdef CFG_IPC_VER_V10
    00455 #error "MU-MIMO cannot be compiled for old IPC"
    00456 #endif
    00458 #if RW_USER_MAX > 3
    00459 #define IPC_IRQ_E2A_USER_MSK       0xF
    00460 #elif RW_USER_MAX > 2
    00461 #define IPC_IRQ_E2A_USER_MSK       0x7
    00462 #else
    00463 #define IPC_IRQ_E2A_USER_MSK       0x3
    00464 #endif
    00465
    00467 #define IPC_IRQ_E2A_AC0_OFT        7
    00469 #define IPC_IRQ_E2A_AC0_MSK       (IPC_IRQ_E2A_USER_MSK << IPC_IRQ_E2A_AC0_OFT)
    00471 #define IPC_IRQ_E2A_AC1_OFT       (IPC_IRQ_E2A_AC0_OFT + RW_USER_MAX)
    00473 #define IPC_IRQ_E2A_AC1_MSK       (IPC_IRQ_E2A_USER_MSK << IPC_IRQ_E2A_AC1_OFT)
    00475 #define IPC_IRQ_E2A_AC2_OFT       (IPC_IRQ_E2A_AC1_OFT + RW_USER_MAX)
    00477 #define IPC_IRQ_E2A_AC2_MSK       (IPC_IRQ_E2A_USER_MSK << IPC_IRQ_E2A_AC2_OFT)
    00479 #define IPC_IRQ_E2A_AC3_OFT       (IPC_IRQ_E2A_AC2_OFT + RW_USER_MAX)
    00481 #define IPC_IRQ_E2A_AC3_MSK       (IPC_IRQ_E2A_USER_MSK << IPC_IRQ_E2A_AC3_OFT)
    00483 #define IPC_IRQ_E2A_BCN_OFT       (IPC_IRQ_E2A_AC3_OFT + RW_USER_MAX)
    00485 #define IPC_IRQ_E2A_BCN_MSK       CO_BIT(IPC_IRQ_E2A_BCN_OFT)
    00486
    00487 #define IPC_IRQ_E2A_AC_TXCFM     (IPC_IRQ_E2A_AC0_MSK | IPC_IRQ_E2A_AC1_MSK | \
    00488                                    IPC_IRQ_E2A_AC2_MSK | IPC_IRQ_E2A_AC3_MSK)
    00489
    00491 #if !NX_BEACONING || (NX_BCN_AUTONOMOUS_TX && !NX_UMAC_PRESENT)
    00492 #define IPC_IRQ_E2A_BCN_TXCFM      0
    00493 #else
    00494 #define IPC_IRQ_E2A_BCN_TXCFM      (0x01 << IPC_IRQ_E2A_BCN_OFT)
    00495 #endif
    00496
    00498 #define IPC_IRQ_E2A_TXCFM          (IPC_IRQ_E2A_AC_TXCFM | IPC_IRQ_E2A_BCN_TXCFM)
    00499
    00500 #else
    00501
    00502 #if !NX_BEACONING || (NX_BCN_AUTONOMOUS_TX && !NX_UMAC_PRESENT)
    00503 #define IPC_IRQ_E2A_TXCFM          ((1 << 4) - 1 ) << IPC_IRQ_E2A_TXCFM_POS
    00504 #else
    00505 #define IPC_IRQ_E2A_TXCFM          ((1 << 5) - 1 ) << IPC_IRQ_E2A_TXCFM_POS
    00506 #endif
    00507
    00508 #endif /* RW_MUMIMO_TX_EN */
    00509
    00510
    00512 #define IPC_IRQ_E2A_UNSUP_RX_VEC CO_BIT(7)
    00514 #define IPC_IRQ_E2A_RADAR       CO_BIT(6)
    00516 #define IPC_IRQ_E2A_TBTT_SEC    CO_BIT(5)
    00518 #define IPC_IRQ_E2A_TBTT_PRIM   CO_BIT(4)
    00520 #define IPC_IRQ_E2A_RXDESC      CO_BIT(3)
    00522 #define IPC_IRQ_E2A_MSG_ACK     CO_BIT(2)
    00524 #define IPC_IRQ_E2A_MSG         CO_BIT(1)
    00526 #define IPC_IRQ_E2A_DBG         CO_BIT(0)
    00528 #define IPC_IRQ_E2A_ALL         ( IPC_IRQ_E2A_TXCFM         \
    00529                                 | IPC_IRQ_E2A_RXDESC        \
    00530                                 | IPC_IRQ_E2A_MSG_ACK       \
    00531                                 | IPC_IRQ_E2A_MSG           \
    00532                                 | IPC_IRQ_E2A_DBG           \
    00533                                 | IPC_IRQ_E2A_TBTT_PRIM     \
    00534                                 | IPC_IRQ_E2A_TBTT_SEC      \
    00535                                 | IPC_IRQ_E2A_RADAR         \
    00536                                 | IPC_IRQ_E2A_UNSUP_RX_VEC)
    00537
    00539
    00541
    00542 #endif // _IPC_SHARED_H_
    00543