# dpereira
# Wed Jan 15 13:23:21 CET 2020
# CONFIG=config_STA_1x1_CBW40_LDPC
# PROC=RISCV
# FPGA_V6=
# FPGA_V7=1
# REFIP=40970
# DOC=40970
# MAC=40970
# MODEM=40970
# HWCOMMON=40970
################################################################################
# Package deliverables
################################################################################
This package contains the following deliverables

  M1908.MAC   Updated version of 802.11ax MAC Hardware
  M1908.MDM   Updated version of 802.11ax 1x1 40MHz Hardware Modem
  M1908.HWTB  Updated version of 802.11ax 1x1 40MHz Full system hardware testbench
  M1908.FPGA  Updated version of 802.11ax FPGA V7 platform with RISCV CPU (MAC+MODEM+platform)

NOTE: The RISCV CPU IP is not provided.

that can be found at the following relative locations:

  M1908.MAC.HW    MAC     (RTL)            ./WLAN_HE_REF_IP/HW/IPs/HW/MAC/Src
  M1908.MAC.HW    MAC     (Documentation)  ./Documents/Specifications
  M1908.MDM.HW    MDM     (RTL)            ./WLAN_HE_REF_IP/HW/IPs/HW/Modem/Src
  M1908.MDM.HW    MDM     (Documentation)  ./Documents/Specifications
  M1908.REF.TB    HWTB    (MAC+MODEM TB)   ./WLAN_HE_REF_IP/HW/SIMS
  M1908.REF.TB    HWTB    (Documentation)  ./Documents/Specifications
  M1908.FPGA      FPGA    (FPGA V7)        ./WLAN_HE_REF_IP/HW/SB/rw_nx_v7

  Moreover a FPGA reference platform is delivered as well.
  This FPGA reference platform is not part of the IP and therefore comes without any warranty.
  It can be used as a reference for FPGA development.

################################################################################
# Package organization
################################################################################
This package contains the WLAN_HE_REF_IP project.

It provides a system level testbench including the Modem IP, the
MAC IP, the RISCV and its sybsytem, a Catena RF model, the Catena radio controller,
the converter models and the AHB slave/master models. This testbench is used to 
run system regression.
This project also contains the environment for complete system ASIC synthesis

################################################################################
# Requirements
################################################################################

 This package has been tested in the following environment :

 Hardware:

  o 3.4 GHz Quad-core i7-2600 PC
  o 64 bits-Linux 2.6.18-274.el5

  Note: this package contains some compiled runtime libraries, you might need to
  regenerate them if you use another workstation architecture.

 System Tools:

   o Python > 2.5
   o Bash > 3.2.25(1)
   o Perl > v5.8.8
   o Recent Flex and YACC
   o Recent (>4.1.2) GCC compiler with C,C++ languages enabled

   Note: this package contains scripts that assume bash program as the default
   script interpreter (#!/bin/sh), you might need to change some scripts if you
   use another workstation architecture.

 CAD Tools:

   o Cadence IUS14.10
   o Synopsys D2014.09SP4
   o MATLAB compiler runtime libraries
   o Xilinx ISE+EDK 14.4 Design Suite (for Virtex6 target)
   o Synopsys Synplify pro 2015.03-1
   o Xilinx Vivado 2016.02 (for Virtex7 target)


################################################################################
# Preliminary preparation
################################################################################
After unpacking the archive, you will need to install the OVL package and edit some files
in order to fit the three projects with your work environment.

o edit 'setup.sh':

 A setup script called 'setup.sh' is provided to initialize the different
 projects with your environment.

 First, edit the 'setup.sh' script and change the following variables according to
 your environment:

 LM_LICENSE_FILE : licenses path
 LD_LIBRARY_PATH : tools runtime libraries path
 PATH            : tools executables path

o edit WLAN_HE_REF_IP/HW/env/SYNTH/library_setup.tcl

  This script is parsed by the synopsys dc_shell tcl interpreter, you have to
  edit this file and change the variables in order to use your founder target
  library.

################################################################################
# WLAN_HE_REF_IP PROJECT SETUP
################################################################################

The WLAN_HE_REF_IP project setup is performed by setting the environment variable
'PROJECT' to the 'WLAN_HE_REF_IP' value and sourcing the 'setup.sh' script.

  setup:bash> cd <unpacked directory>
  setup:bash> export PROJECT=WLAN_HE_REF_IP
  setup:bash> source setup.sh

################################################################################
# WLAN_HE_REF_IP UVM SIMULATION
################################################################################

  * Change directory to the simulation workarea
  uvm:bash> cd $SOURCESLIB/SIMS_UVM/run

  * Build DPI objects
  uvm:bash> ./simulate.bash -config config_STA_1x1_CBW40_LDPC -comp_dpi

  * Launch the regression
  uvm:bash> ./simulate.bash -config config_STA_1x1_CBW40_LDPC -nodb -f wlan_regression.list -cpu

  after a while, you should see the following report indicating
  that the WLAN_HE_REF_IP regression has successfully passed.

  out> Simulation Results
  out>
  out>test_wlan_regs_reset PASSED
  out>test_wlan_regs_rw PASSED
  out>test_wlan_rx_ampdu_frame PASSED
  out>...

################################################################################
# WLAN_HE_REF_IP ASIC SYNTHESIS
################################################################################

  * Ensure that you have edited the 'library_setup.tcl' file
    to point to your founder target library.
  asicsyn:bash> vi $SOURCESLIB/env/SYNTH/library_setup.tcl

  * Change directory to the synthesis workarea
  asicsyn:bash>cd $TOP11AXDIR/rw_he_top_cpu/synth/ASIC

  * Build the synthesis workarea, you can have as much independant working
    area than you want by providing a suffix to the RW_SYNDIR variable,
    for instance with the 'dev' suffix:
  asicsyn:bash> RW_SYNDIR=dev ./asic_run.sh -i

  * Launch the synthesis process
  asicsyn:bash> RW_SYNDIR=dev ./asic_run.sh -c -lib 40nmLP -config config_STA_1x1_CBW40_LDPC -s

  * Reports are available in the ./dc_work.dev/reports directory

################################################################################
# WLAN_REF_IP CEVA-V7 SYNTHESIS
################################################################################

  The WLAN_HE_REF_IP projects targets the CEVA-FPGA-V7 board.

  Before starting the bitmap generation, it is supposed that RW_WLAN_REF_IP project has been correctly
  set as well as the EDA tools. It is also supposed that the RISCV has been generated with the right configuration
  FPGA Setup

  * It is assumed that Synplify and Xilinx tools are correctly set up.

  * Move to the synthesis directory located in the corresponding FPGA top:

    v7syn:bash> cd $SOURCESLIB/SB/rw_nx_v7/synth/FPGA

    All synthesis steps through the './fpga.sh' shall be done at this directory location.

  * A script fpga.sh is provided to support all steps of the FPGA V7 build.
    v7syn:bash> ./fpga.sh help

  * The design targeting the FPGA requires several memories, xilinx memory views shall be generated first before others steps.
    This step shall be repeated each time the geometry of a memory is changed.
    v7syn:bash> ./fpga.sh build_coregen

  * The design targeting the FPGA requires Xilinx PCIe subsystem, it shall be generated before synthesis steps.
    This step shall be repeated each time the PCIe subsystem is changed.
    v7syn:bash> ./fpga.sh build_vivado

  * Create the workarea. You can have as many workareas as you want.
    The workarea is a directory named 'work.$RW_SYNDIR' where are run synthesis tools, it also contains initialized template files (such fdc and xdc constraints).
    v7syn:bash> RW_SYNDIR=myworkarea CONFIG=config_STA_1x1_CBW40_LDPC PROC=RISCV ./fpga.sh init

  * Build the concatened file for synthesis. This step collects the different IPs and collect them into a single verilog file.
    v7syn:bash> RW_SYNDIR=myworkarea CONFIG=config_STA_1x1_CBW40_LDPC PROC=RISCV ./fpga.sh build_sources

  * Do the logic synthesis.
    v7syn:bash> RW_SYNDIR=myworkarea CONFIG=config_STA_1x1_CBW40_LDPC PROC=RISCV SYNPLIFY_LOCAL=1 ./fpga.sh synthesis
    NOTE: In the reference script, the synthesis is done using Synplify Pro.

  * Do the place/route and bitfile generation.
    v7syn:bash> RW_SYNDIR=myworkarea CONFIG=config_STA_1x1_CBW40_LDPC PROC=RISCV VIVADO_LOCAL=1 ./fpga.sh par

  The generated bit file is available here : work.<RW_SYNDIR>.RISCV.STA_1x1_CBW40_LDPC/par/rw_nx_v7.bit
