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# /space/home/slher/rel/Beken/v6_4_5/macsw/plf/refip/src/driver/phy/phy_custom_rf.c

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    00001
    00014 #include "rwnx_config.h"
    00015 #include "phy.h"
    00016 #include "dbg.h"
    00017
    00018 #include "hal_machw.h"
    00019 #include "reg_mac_core.h"
    00020
    00021 #if NX_MDM_VER < 30
    00022 #include "reg_mdm_stat.h"
    00023 #include "reg_mdmdsss_cfg.h"
    00024 #endif
    00025 #include "reg_mdm_cfg.h"
    00026
    00027 #include "reg_riu.h"
    00028 #include "reg_rc.h"
    00029 #include "reg_macbypass.h"
    00030
    00031 #include "crm.h"
    00032
    00033 #include "rd.h"
    00034 #include "uf.h"
    00035
    00036 #if NX_UF_EN
    00037 #define RXV_REG_MIN_VERS    2
    00038 #endif
    00039
    00042 struct phy_custom_cfg_tag
    00043 {
    00044 };
    00045
    00047 struct phy_env_tag
    00048 {
    00050     struct phy_custom_cfg_tag cfg;
    00052     struct mac_chan_op chan;
    00053 };
    00054
    00056 struct phy_env_tag phy_env;
    00057
    00059 #define __RIU_RADARFIFO_ADDR 0x60C04000
    00060
    00070 static void custom_rf_set_channel(uint8_t band, uint16_t freq1, uint8_t chantype)
    00071 {
    00072     // Add the RF/ADC/DAC/etc. configuration code for channel switch
    00073 }
    00074
    00084 static void riu_pssel_set(uint16_t freq, uint16_t freq1, uint8_t chantype)
    00085 {
    00086     unsigned int pssel;
    00087
    00091     if (chantype == PHY_CHNL_BW_40)
    00092     {
    00093         // pssel = 1 or 2
    00094         pssel = freq < freq1 ? 1 : 2;
    00095     }
    00096     else if (chantype == PHY_CHNL_BW_80)
    00097     {
    00098         // pssel = 0, 1, 2 or 3
    00099         int _offs = freq1 - freq;
    00100         if (_offs > 0)
    00101             pssel = _offs > 10 ? 0 : 1;
    00102         else
    00103             pssel = -_offs > 10 ? 3 : 2;
    00104     }
    00105     else
    00106     {
    00107         pssel = 0;
    00108     }
    00109
    00110     riu_psselect_setf(pssel);
    00111 }
    00112
    00122 static void mdm_primary_set(uint16_t freq, uint16_t freq1, uint8_t chantype)
    00123 {
    00124     #if NX_MDM_VER >= 30
    00125     unsigned int primary;
    00126
    00127     if (chantype == PHY_CHNL_BW_40)
    00128     {
    00129         primary = freq < freq1 ? 0 : 1;
    00130     }
    00131     else if (chantype == PHY_CHNL_BW_80)
    00132     {
    00133         primary = 0; // TBD
    00134     }
    00135     else
    00136     {
    00137         primary = 0;
    00138     }
    00139
    00140     mdm_primaryind_set(primary);
    00141     #endif
    00142 }
    00143
    00155 static void mdm_set_channel(uint8_t band, uint16_t freq, uint16_t freq1, uint8_t chantype,
    00156                             uint8_t flags)
    00157 {
    00158     // Reset the MDM/RIU before configuration
    00159     crm_mdm_reset();
    00160
    00161     /*
    00162      *************************************************************************************
    00163      * Band-dependent (2.4G, 5G) settings
    00164      *************************************************************************************
    00165      */
    00166     // By default we consider we won't be on a DFS channel
    00167     #if NX_RADAR_DETECT
    00168     riu_radardeten_setf(0); // Disable radar detection
    00169     crm_radartimclkforce_setf(0); // Disable radar timer clock
    00170     riu_irqmacradardeten_setf(0); // disable radar detection interrupt
    00171     #endif
    00172     #if NX_MAC_HE
    00173     nxmac_disable_tbru_26_resp_setf(0); // Allow RU26
    00174     #endif
    00175     if(band == PHY_BAND_5G)
    00176     {
    00177         rc_rf_sel_2g4_setf(0);
    00178         nxmac_abgn_mode_setf(MODE_802_11AC_5);
    00179         mdm_rxdsssen_setf(0);
    00180         riu_ofdmonly_setf(1);   // AGC detection OFDM only
    00181         #if NX_RADAR_DETECT || NX_MAC_HE
    00182         if (flags & CHAN_RADAR)
    00183         {
    00184             #if NX_RADAR_DETECT
    00185             riu_radardeten_setf(1); // Enable radar detection
    00186             crm_radartimclkforce_setf(1); // Enable radar timer clock
    00187             riu_irqmacradardeten_setf(1); // Enable radar detection interrupt
    00188             #endif
    00189             #if NX_MAC_HE
    00190             nxmac_disable_tbru_26_resp_setf(1); // No RU26 when tuned to a DFS channel
    00191             #endif
    00192         }
    00193         #endif
    00194         riu_rwnxagcevt3_set(0);     /* write 0 to disable DSSS detection correlator */
    00195     }
    00196     else
    00197     {
    00198         rc_rf_sel_2g4_setf(1);
    00199         nxmac_abgn_mode_setf(MODE_802_11N_2_4);
    00200         mdm_rxdsssen_setf(1);
    00201         riu_ofdmonly_setf(0);   // AGC detection OFDM and DSSS
    00202         riu_rwnxagcevt3_set(RIU_RWNXAGCEVT3_RESET);/* write default to enable DSSS detection correlator */
    00203     }
    00204
    00205     /*
    00206      *************************************************************************************
    00207      * Frequency-dependent settings
    00208      *************************************************************************************
    00209      */
    00210     #if NX_MDM_VER >= 30
    00211     // For symbol clock error compensation in HE TB
    00212     mdm_invcarrierfreq_setf((1 << 26) / freq1);
    00213     #endif
    00214
    00215     /*
    00216      *************************************************************************************
    00217      * Bandwidth-dependent settings
    00218      *************************************************************************************
    00219      */
    00220     // Set PSSEL
    00221     riu_pssel_set(freq, freq1, chantype);
    00222     // Set Primary Channel in MDM
    00223     mdm_primary_set(freq, freq1, chantype);
    00224     // Configure maximum BW
    00225     mdm_txcbwmax_setf(chantype);
    00226     nxmac_max_supported_bw_setf(chantype);
    00227     // Put default values
    00228     mdm_fdoctrl0_set(MDM_FDOCTRL0_RESET);
    00229     #if NX_MDM_VER < 30
    00230     mdm_tbectrl2_set(0x00007F05);
    00231     #else
    00232     mdm_conf_bw_setf(chantype);
    00233     mdm_rxcbwmax_setf(chantype);
    00234     // To be uncommented when NX_MDM_VER=30 supports 80 MHz
    00235     //mdm_tbectrl2_set(MDM_TBECTRL2_RESET);
    00236     #endif
    00237     #if NX_MDM_VER >= 22
    00238     mdm_smoothforcectrl_set(0);
    00239     #else
    00240     mdm_smoothctrl_set(0x01880C06);
    00241     #endif
    00242
    00243     //  3us for TX RAMPUP <=> TXRFRAMPUP = 360
    00244     if (chantype == PHY_CHNL_BW_20)
    00245     {
    00246         #if NX_MDM_VER < 30
    00247         mdm_txstartdelay_setf(180);
    00248         mdm_txctrl1_pack(0, 0, 28, 48);
    00249         // TBE for 60MHz
    00250         mdm_tbe_count_adjust_20_setf(0);
    00251         mdm_txctrl3_pack(720, 1080);
    00252         mdm_dcestimctrl_pack(0, 0, 0, 15, 15);
    00253         // For FPGA, divide value by 2 due to timing constraints
    00254         mdm_waithtstf_setf(7);
    00255         #else
    00256         mdm_txstartdelay_setf(384);
    00257         mdm_txctrl1_pack(64, 96);
    00258         // TBE for 120MHz
    00259         mdm_tbe_count_adjust_20_setf(4);
    00260         mdm_dcestimctrl_pack(0, 2, 10, 15);
    00261         // For FPGA, divide value by 2 due to timing constraints
    00262         mdm_waithtstf_setf(7);
    00263         mdm_tdsyncoff20_setf(25);
    00264         #endif
    00265
    00266         #if NX_MDM_VER < 30
    00267         mdm_tddchtstfmargin_setf(6);
    00268         #else
    00269         mdm_tddchtstfmargin_setf(1);
    00270         #endif
    00271
    00272         // No ACI margin in BW=20MHz due to latency on HTSIG decoding
    00273         riu_rwnxagcaci20marg0_set(0);
    00274         riu_rwnxagcaci20marg1_set(0);
    00275         riu_rwnxagcaci20marg2_set(0);
    00276
    00277         #if NX_MDM_VER >= 30
    00278         // Increase DC convergence due to Karst RF performance
    00279         riu_dccenteredholdtime50ns_setf(15);
    00280         #endif
    00281     }
    00282     else
    00283     {
    00284
    00285         #if NX_MDM_VER < 30
    00286         // TBE for 120MHz
    00287         mdm_tbe_count_adjust_20_setf(2);
    00288         mdm_txstartdelay_setf(360);
    00289         mdm_txctrl3_pack(1440, 2160);
    00290         #endif
    00291
    00292         if (chantype == PHY_CHNL_BW_40)
    00293         {
    00294             #if NX_MDM_VER < 30
    00295             mdm_txctrl1_pack(0, 39, 82, 96);
    00296             mdm_rxtdctrl0_pack(18, 64, 252, 13);
    00297             mdm_dcestimctrl_pack(0, 0, 8, 30, 31);
    00298             // For FPGA, divide value by 2 due to timing constraints
    00299             mdm_waithtstf_setf(15);
    00300             #else
    00301             mdm_txstartdelay_setf(384);
    00302             mdm_txctrl1_pack(64, 96);
    00303             mdm_dcestimctrl_pack(0, 3, 16, 31);
    00304             // For FPGA, divide value by 2 due to timing constraints
    00305             mdm_waithtstf_setf(15);
    00306             mdm_tbe_count_adjust_20_setf(4);
    00307             mdm_tdsyncoff20_setf(24);
    00308             #endif
    00309
    00310             #if NX_MDM_VER < 30
    00311             mdm_tddchtstfmargin_setf(6);
    00312             #else
    00313             mdm_tddchtstfmargin_setf(1);
    00314             #endif
    00315         }
    00316         else // chantype == PHY_CHNL_BW_80
    00317         {
    00318             #if NX_MDM_VER < 30
    00319             mdm_txctrl1_pack(22, 60, 105, 120);
    00320             mdm_rxtdctrl0_pack(18, 64, 247, 23);
    00321             mdm_dcestimctrl_pack(0, 0, 38, 43, 63);
    00322             // For FPGA, divide value by 2 due to timing constraints
    00323             mdm_waithtstf_setf(31);
    00324             #endif
    00325
    00326             mdm_tddchtstfmargin_setf(14);
    00327
    00328             #if NX_MDM_VER >= 22 && NX_MDM_VER < 30
    00329             mdm_cfgvhtsts2smoothforce_setf(1);
    00330             mdm_cfgvhtsts2smooth_setf(2);
    00331             #else
    00332             mdm_smoothctrl_set(0x018E0C06);
    00333             #endif
    00334             mdm_tbectrl2_set(0x00007F03);
    00335         }
    00336
    00337         // Set back default ACI margin
    00338         riu_rwnxagcaci20marg0_set(RIU_RWNXAGCACI20MARG0_RESET);
    00339         riu_rwnxagcaci20marg1_set(RIU_RWNXAGCACI20MARG1_RESET);
    00340         riu_rwnxagcaci20marg2_set(RIU_RWNXAGCACI20MARG2_RESET);
    00341
    00342         #if NX_MDM_VER >= 30
    00343         // Set back default DC parameters for BW > 20MHz
    00344         riu_dccenteredholdtime50ns_setf(RIU_DCCENTEREDHOLDTIME50NS_RST);
    00345         #endif
    00346
    00347     }
    00348
    00349     #if NX_MDM_VER >= 21
    00350     /* Reset RX IQ compensation if available */
    00351     if (riu_iqcomp_getf())
    00352     {
    00353         riu_iqestiterclr_setf(1);
    00354     }
    00355     #endif /* NX_MDM_VER >= 21 */
    00356 }
    00357
    00370 static void phy_hw_set_channel(uint8_t band, uint16_t freq, uint16_t freq1,
    00371                                uint8_t chantype, uint8_t flags, uint8_t index)
    00372 {
    00373     dbg(D_INF D_PHY "%s: band=%d freq=%d freq1=%d chantype=%d sx=%d\n",__func__,band,freq,freq1,chantype,index);
    00374
    00375     /*
    00376      *************************************************************************************
    00377      * Clock configuration
    00378      *************************************************************************************
    00379      */
    00380     crm_clk_set(chantype);
    00381
    00382     /*
    00383      *************************************************************************************
    00384      * MODEM/RIU configuration
    00385      *************************************************************************************
    00386      */
    00387     mdm_set_channel(band, freq, freq1, chantype, flags);
    00388
    00389     /*
    00390      *************************************************************************************
    00391      * RF/RF board configuration
    00392      *************************************************************************************
    00393      */
    00394     custom_rf_set_channel(band, freq1, chantype);
    00395 }
    00396
    00404 static void custom_rf_init(const struct phy_custom_cfg_tag *cfg)
    00405 {
    00406     // Add the initial configuration of the RF/ADC/DAC/etc.
    00407 }
    00408
    00416 static void mdm_init(const struct phy_custom_cfg_tag *cfg)
    00417 {
    00418     // Check if we are compiled for this version of the PHY
    00419     ASSERT_ERR((mdm_major_version_getf() + 2) * 10 + mdm_minor_version_getf()
    00420                                                                  == NX_MDM_VER);
    00421
    00422     // Reset the MDM/RIU before configuration
    00423     crm_mdm_reset();
    00424
    00425     /*
    00426      *************************************************************************************
    00427      * MODEM configuration
    00428      *************************************************************************************
    00429      */
    00430     // Supported features
    00431     mdm_rxmode_set(MDM_RXMMEN_BIT | MDM_RXDSSSEN_BIT);
    00432     mdm_rxnssmax_setf(mdm_nss_getf() - 1);
    00433     mdm_rxndpnstsmax_setf(mdm_nsts_getf() - 1);
    00434     mdm_rxldpcen_setf(mdm_ldpcdec_getf());
    00435     mdm_rxvhten_setf(phy_vht_supported());
    00436     mdm_rxstbcen_setf(1);
    00437     #if NX_MDM_VER < 30
    00438     mdm_rxgfen_setf(1);
    00439     mdm_rxmumimoen_setf(mdm_mumimorx_getf());
    00440     mdm_rxmumimoapeplenen_setf(mdm_mumimorx_getf());
    00441     #else
    00442     mdm_rxdcmen_setf(mdm_he_getf());
    00443     mdm_rxheen_setf(mdm_he_getf());
    00444     mdm_rxvhtmumimoen_setf(mdm_vht_getf() & mdm_mumimorx_getf());
    00445     mdm_rxhemumimoen_setf(mdm_he_getf() & mdm_mumimorx_getf());
    00446     #endif
    00447
    00448     // Set DSSS precomp
    00449     mdm_precomp_setf(45);
    00450
    00451     #if NX_MDM_VER == 20
    00452     #if RW_NX_LDPC_DEC
    00453     // Set LDPC table selection for FPGA limitation
    00454     mdm_ldpcdectablesel_setf(2);
    00455     #endif
    00456     #endif
    00457
    00458     // Allow GF/SGI/STBC (bit14 reset) - TEMPORARY!!!!
    00459     mdm_rxframeviolationmask_setf(0xFFFFBFFF);
    00460
    00461     mdm_txmode_set(MDM_TXSTBCEN_BIT | MDM_TXGFEN_BIT  |
    00462                    MDM_TXMMEN_BIT   | MDM_TXDSSSEN_BIT);
    00463     mdm_txnssmax_setf(mdm_nss_getf() - 1);
    00464     mdm_ntxmax_setf(mdm_ntx_getf() - 1);
    00465     mdm_txcbwmax_setf(mdm_chbw_getf());
    00466     mdm_txldpcen_setf(mdm_ldpcenc_getf());
    00467     mdm_txvhten_setf(phy_vht_supported());
    00468     #if NX_MDM_VER >= 30
    00469     mdm_txheen_setf(phy_he_supported());
    00470     mdm_tdfocpeslopeen_setf(1);
    00471     #endif
    00472     mdm_txmumimoen_setf(mdm_mumimotx_getf());
    00473
    00474     #if NX_MDM_VER < 30
    00475     /* AGC reset mode
    00476      don't turn off RF if rxreq de-asserted for few cycles after a RXERR */
    00477     mdm_rxtdctrl1_set(mdm_rxtdctrl1_get()|1);
    00478     #endif
    00479
    00480     /* Enable automatic smoothing filter selection from SNR, then disable force */
    00481     #if NX_MDM_VER < 22
    00482     mdm_cfgsmoothforce_setf(0);
    00483     #endif
    00484
    00485     #if NX_MDM_VER < 30
    00486     if (mdm_nss_getf() == 1)
    00487     {
    00488         /* limit NDBPSMAX to 1x1 80 MCS7 LGI(292.5Mb/s) / SGI (325.0Mb/s) */
    00489         mdm_rxctrl1_set(0x04920492);
    00490     }
    00491     else
    00492     {
    00493         #if defined(CFG_VIRTEX6)
    00494         /* limit NDBPSMAX to 2x2 80 MCS4 LGI(351Mb/s) / SGI (390.0Mb/s) */
    00495         mdm_rxctrl1_set(0x057C057C);
    00496         #elif defined(CFG_VIRTEX7)
    00497         /* No limitation on VIRTEX7 platform */
    00498         mdm_rxctrl1_set(0x0C300C30);
    00499         #endif
    00500     }
    00501     #else
    00502     mdm_txtdsfoctrl_set(0x10000000);
    00503     mdm_txtdcfoctrl_set(0x10000000);
    00504     mdm_rxctrl5_set(0x00670780);
    00505     mdm_tdfoctrl0_set(0x00340100);
    00506     #endif
    00507
    00508     /*
    00509      *************************************************************************************
    00510      * RIU configuration
    00511      *************************************************************************************
    00512      */
    00513     /* Enable RC clock */
    00514     crm_rcclkforce_setf(1);
    00515
    00516     /* RC delays */
    00517     rc_hw_tx_delay_set(0xa0);
    00518
    00519     #if NX_MDM_VER >= 21
    00520     /* Enable RX IQ compensation if available */
    00521     if (riu_iqcomp_getf())
    00522     {
    00523         riu_rxiqphaseesten_setf(1);
    00524         riu_rxiqgainesten_setf(1);
    00525         riu_rxiqphasecompen_setf(1);
    00526         riu_rxiqgaincompen_setf(1);
    00527         riu_iqestiterclr_setf(1);
    00528     }
    00529     #endif /* NX_MDM_VER >= 21 */
    00530
    00531     /* limit RIU to 1 or 2 antenna active depending on modem capabilities */
    00532     if (mdm_nss_getf() == 2)
    00533     {
    00534         riu_activeant_setf(3);
    00535         riu_combpathsel_setf(3);
    00536     }
    00537     else
    00538     {
    00539         riu_activeant_setf(1);
    00540         /* limit AGC with a single antenna (path0) */
    00541         riu_combpathsel_setf(1);
    00542     }
    00543
    00544     // Tx Digital gain
    00545     #if NX_MDM_VER < 30
    00546     riu_rwnxfectrl0_set(0x001A1A1A);
    00547     if (mdm_ntx_getf() == 2)
    00548         riu_rwnxfectrl1_set(0x001A1A1A);
    00549     #else
    00550     riu_rifsdeten_setf(0);
    00551     riu_rwnxfectrl0_set(0x00343434);
    00552     if (mdm_ntx_getf() == 2)
    00553         riu_rwnxfectrl1_set(0x00343434);
    00554
    00555     /* disable the riu dccentered compensation */
    00556     riu_dccenteredtype_setf(0);
    00557     #endif
    00558
    00559     riu_crossupthrqdbm_setf(0x200); /* write 0x200 to disable AGC cross-up */
    00560     riu_crossdnthrqdbm_setf(0x200); /* write 0x200 to disable AGC cross-down */
    00561
    00562     riu_rwnxagcccatimeout_set(8000000); // 100ms
    00563     riu_irqmacccatimeouten_setf(1);
    00564
    00565     /* Enable HW antenna selection */
    00566     riu_rxpathselfromreg_setf(0);
    00567
    00568     /*
    00569      *************************************************************************************
    00570      * MACBYPASS configuration
    00571      *************************************************************************************
    00572      */
    00573     #if NX_MDM_VER >= 30
    00574     macbyp_clken_set(1); // enable clock
    00575     #endif
    00576     macbyp_trigger_set(0x00000012);
    00577     macbyp_ctrl_set(0x00000100);
    00578
    00579     #if NX_UF_EN
    00580     if (macbyp_version_get() >= RXV_REG_MIN_VERS)
    00581     {
    00582         macbyp_clken_set(1); // enable clock
    00583         macbyp_int3_gen_setf(0x07);// configure interrupt generation
    00584         macbyp_mode_setf(1); //set mode RX
    00585     }
    00586     #endif
    00587 }
    00588
    00596 static void phy_hw_init(const struct phy_custom_cfg_tag *cfg)
    00597 {
    00598     /*
    00599      *************************************************************************************
    00600      * MODEM/RIU configuration
    00601      *************************************************************************************
    00602      */
    00603     mdm_init(cfg);
    00604
    00605     /*
    00606      *************************************************************************************
    00607      * RF/RF board configuration
    00608      *************************************************************************************
    00609      */
    00610     custom_rf_init(cfg);
    00611
    00612     /*
    00613      *************************************************************************************
    00614      * Set a default channel
    00615      *************************************************************************************
    00616      */
    00617     phy_hw_set_channel(PHY_BAND_5G, 5180, 5180, PHY_CHNL_BW_20, 0, 0);
    00618 }
    00619
    00620 void phy_init(const struct phy_cfg_tag *config)
    00621 {
    00622     const struct phy_custom_cfg_tag *cfg = (const struct phy_custom_cfg_tag *)&config->parameters;
    00623
    00624     phy_hw_init(cfg);
    00625
    00626     phy_env.cfg               = *cfg;
    00627     phy_env.chan.band         = PHY_BAND_5G;
    00628     phy_env.chan.type         = PHY_CHNL_BW_OTHER;
    00629     phy_env.chan.prim20_freq  =
    00630     phy_env.chan.center1_freq =
    00631     phy_env.chan.center2_freq = PHY_UNUSED;
    00632 }
    00633
    00634 void phy_mdm_isr(void)
    00635 {
    00636     #if NX_UF_EN
    00637     if (macbyp_int3_state_getf())
    00638     {
    00639         //Indicate that an unsupported HT frame has been capture
    00640         uf_event_ind();
    00641
    00642         //interrupt 3 ack
    00643         macbyp_int3_ack_clearf(1);
    00644     }
    00645     #endif
    00646 }
    00647
    00651 void phy_rc_isr(void)
    00652 {
    00653     uint32_t irq_status = riu_rwnxmacintstatmasked_get();
    00654
    00655     riu_rwnxmacintack_clear(irq_status);
    00656
    00657     #if NX_RADAR_DETECT
    00658     if (irq_status & RIU_IRQMACRADARDETMASKED_BIT)
    00659     {
    00660         PROF_RADAR_IRQ_SET();
    00661         rd_event_ind(PHY_PRIM);
    00662         PROF_RADAR_IRQ_CLR();
    00663     }
    00664     #endif
    00665
    00666     if (irq_status & RIU_IRQMACCCATIMEOUTMASKED_BIT)
    00667         crm_mdm_reset();
    00668
    00669     ASSERT_REC(!(irq_status & RIU_IRQMACCCATIMEOUTMASKED_BIT));
    00670 }
    00671
    00672 void phy_get_version(uint32_t *version_1, uint32_t *version_2)
    00673 {
    00674     *version_1 = mdm_hdmconfig_get();
    00675     // TODO Add version reading for other PHY elements than modem.
    00676     *version_2 = mdm_hdmversion_get();
    00677 }
    00678
    00679 void phy_set_channel(const struct mac_chan_op *chan, uint8_t index)
    00680 {
    00681     if (index > 0)
    00682     {
    00683         dbg(D_ERR D_PHY "%s: radio %d does not exist\n", __func__, index);
    00684         return;
    00685     }
    00686
    00687     if (phy_env.chan.band == chan->band &&
    00688         phy_env.chan.type == chan->type &&
    00689         phy_env.chan.flags == chan->flags &&
    00690         phy_env.chan.prim20_freq == chan->prim20_freq &&
    00691         phy_env.chan.center1_freq == chan->center1_freq &&
    00692         phy_env.chan.center2_freq == chan->center2_freq)
    00693     {
    00694         dbg(D_INF D_PHY "%s: Setting same channel, do nothing\n", __func__);
    00695         return;
    00696     }
    00697
    00698     dbg(D_INF D_PHY "%s: c:%d c1:%d bw:%d\n", __func__,
    00699         chan->prim20_freq, chan->center1_freq, (1 << chan->type) * 20);
    00700
    00701     phy_hw_set_channel(chan->band, chan->prim20_freq, chan->center1_freq, chan->type,
    00702                        chan->flags, index);
    00703     phy_env.chan = *chan;
    00704 }
    00705
    00706 void phy_get_channel(struct phy_channel_info *info, uint8_t index)
    00707 {
    00708     if (index > 0)
    00709     {
    00710         dbg(D_ERR D_PHY "%s: radio %d does not exist\n", __func__, index);
    00711     }
    00712     // Map the band, channel type, primary channel index on info1
    00713     info->info1 = phy_env.chan.band | (phy_env.chan.type << 8) | (phy_env.chan.prim20_freq << 16);
    00714     // Map center freq on info2
    00715     info->info2 = phy_env.chan.center1_freq | (phy_env.chan.center2_freq << 16);
    00716 }
    00717
    00718 void phy_stop(void)
    00719 {
    00720     if (nxmac_current_state_getf() != HW_IDLE)
    00721         dbg(D_ERR "%s MAC state != IDLE\n", __func__);
    00722 }
    00723
    00724 uint32_t phy_get_channel_switch_dur(void)
    00725 {
    00726     return 1000;
    00727 }
    00728
    00729 #if NX_RADAR_DETECT
    00730 bool phy_has_radar_pulse(int rd_idx)
    00731 {
    00732
    00733     ASSERT_ERR(rd_idx == PHY_PRIM);
    00734
    00735     return (riu_radfifoempty_getf() == 0);
    00736 }
    00737
    00738 bool phy_get_radar_pulse(int rd_idx, struct phy_radar_pulse *pulse)
    00739 {
    00740     ASSERT_ERR(rd_idx == PHY_PRIM);
    00741
    00742     // Check if FIFO is empty
    00743     if (riu_radfifoempty_getf())
    00744         return (false);
    00745
    00746     pulse->pulse = REG_PL_RD(__RIU_RADARFIFO_ADDR);
    00747
    00748     return (true);
    00749 }
    00750 #endif
    00751
    00752 bool phy_vht_supported(void)
    00753 {
    00754     #if NX_MDM_VER > 20
    00755     return ((mdm_vht_getf() != 0) || (mdm_chbw_getf() > PHY_CHNL_BW_40));
    00756     #else
    00757     return true;
    00758     #endif
    00759 }
    00760
    00761 bool phy_he_supported(void)
    00762 {
    00763     #if NX_MDM_VER < 30
    00764     return false;
    00765     #else
    00766     return (mdm_he_getf() != 0);
    00767     #endif
    00768 }
    00769
    00770 bool phy_uf_supported(void)
    00771 {
    00772     #if NX_UF_EN
    00773     return true ? macbyp_version_get() >= RXV_REG_MIN_VERS : false;
    00774     #else
    00775     return false;
    00776     #endif
    00777 }
    00778
    00779 void phy_uf_enable(bool enable)
    00780 {
    00781     #if NX_UF_EN
    00782     // enable/disable macbypass interrupt line 3
    00783     macbyp_interrupt3_en_setf(enable);
    00784     #endif
    00785 }
    00786
    00787 bool phy_ldpc_tx_supported(void)
    00788 {
    00789     return (mdm_ldpcenc_getf() != 0);
    00790 }
    00791
    00792 bool phy_ldpc_rx_supported(void)
    00793 {
    00794     return (mdm_ldpcdec_getf() != 0);
    00795 }
    00796
    00797 bool phy_bfmee_supported(void)
    00798 {
    00799     return (mdm_bfmee_getf() != 0);
    00800 }
    00801
    00802 bool phy_bfmer_supported(void)
    00803 {
    00804     return (mdm_bfmer_getf() != 0);
    00805 }
    00806
    00807 bool phy_mu_mimo_rx_supported(void)
    00808 {
    00809     return (mdm_mumimorx_getf() != 0);
    00810 }
    00811
    00812 bool phy_mu_mimo_tx_supported(void)
    00813 {
    00814     return (mdm_mumimotx_getf() != 0);
    00815 }
    00816
    00817 #if RW_MUMIMO_RX_EN
    00818 void phy_set_group_id_info(uint32_t membership_addr, uint32_t userpos_addr)
    00819 {
    00820     int i;
    00821
    00822     // Set membership status
    00823     for(i=0; i<MDM_MUMIMO_GROUPID_TAB_COUNT; i++)
    00824     {
    00825         mdm_mumimo_groupid_tab_set(i, co_read32p(membership_addr + 4 * i));
    00826     }
    00827
    00828     // Set user position
    00829     for(i=0; i<MDM_MUMIMO_USERPOSITION_TAB_COUNT; i++)
    00830     {
    00831         mdm_mumimo_userposition_tab_set(i, co_read32p(userpos_addr + 4 * i));
    00832     }
    00833 }
    00834 #endif
    00835
    00836 void phy_set_aid(uint16_t aid)
    00837 {
    00838     #if NX_MDM_VER >= 30
    00839     mdm_hestaid_setf(0, aid);
    00840     mdm_hestaid_setf(1, 0);
    00841     mdm_hestaid_setf(2, 2047);
    00842     #endif
    00843 }
    00844
    00845 uint8_t phy_get_bw(void)
    00846 {
    00847     return (mdm_chbw_getf());
    00848 }
    00849
    00850 uint8_t phy_get_nss(void)
    00851 {
    00852     return (mdm_nss_getf() - 1);
    00853 }
    00854
    00855 uint8_t phy_get_ntx(void)
    00856 {
    00857     return (mdm_ntx_getf() - 1);
    00858 }
    00859
    00860 uint8_t phy_get_nrx(void)
    00861 {
    00862     return (mdm_nrx_getf() - 1);
    00863 }
    00864
    00865 #if RW_BFMER_EN
    00866 uint8_t phy_get_bfr_mem_size(void)
    00867 {
    00868     return (mdm_bfmer_mem_size_getf());
    00869 }
    00870 #endif
    00871
    00872 void phy_get_rf_gain_idx(int8_t *power, uint8_t *idx)
    00873 {
    00874     /* TO BE COMPLETED. For now set idx to power for debug */
    00875     *idx = (uint8_t)*power;
    00876 }
    00877
    00878 void phy_get_rf_gain_capab(int8_t *max, int8_t *min)
    00879 {
    00880     /* TO BE UPDATED with correct value */
    00881     *max = 25; // dBm
    00882     *min = 0;  // dBm
    00883 }
    00884
    00885 #if NX_DEBUG_DUMP
    00886 void phy_get_diag_state(struct dbg_debug_info_tag *dbg_info)
    00887 {
    00888 }
    00889 #endif
    00890
    00891 uint8_t phy_switch_antenna_paths(void)
    00892 {
    00893     uint8_t value = 0;
    00894
    00895     PROF_ANT_DIV_SWITCH_SET();
    00896     PROF_ANT_DIV_SWITCH_CLR();
    00897
    00898     return value;
    00899 }
    00900