> ## cdc_verify

> The aim of this goal is to verify all aspects of clock domain crossings. Review and fix each category of CDC problems separately. The violations can be debugged and fixed in the following order

> 1. Ensure that the setup is clean: analyze and fix violations reported by the following rules

> Clock_info03a, Clock_info03b, Clock_info03c, Clock_info05, Clock_info05b, Clock_converge01, Ar_converge01, Reset_info09a, Ac_resetvalue01, Ac_clockperiod01, Ac_clockperiod02, Ac_clockperiod03, Clock_info15, Setup_port01, Setup_blackbox01, Reset_check03, Reset_check10, Reset_check11, Reset_check12, Ar_syncrstactive01, Ar_syncrstcombo01, Ar_syncrstload01, Ar_syncrstload02, Ar_syncrstpragma01, Ar_syncrstrtl01, FalsePathSetup, Setup_library01

> 2. Ensure that the design has been properly initialized: Review Ac_initstate01 to ensure at least 80% of flops are initialized and uninitialized flops are not important for functional verification (e.g. sometimes memories are not initialized and are initialized during the execution of the design).
> 3. Analyze and fix the unsynchronized crossings reported by Ac_unsync01 and Ac_unsync02 rules
> 4. Analyze and fix other clock and reset synchronization issues reported by the following rules:

> Clock_sync05, Clock_sync06, Ar_unsync01, Ar_asyncdeassert01, Reset_sync02, Reset_sync04

> 5. Analyze and fix convergence issues reported by following rules

> Ac_conv01, Ac_conv02, Ac_conv03, Ac_conv04, Ac_coherency06

> 6. Ensure that crossings functionality is correct: Analyze and fix following rules

> Ac_cdc01a, Ac_datahold01a