#!/bin/sh -e

# default compile command is modelsim unless you set BRC_VLOG_COMPILE
COMPILE_VLOG=${BRC_VERILOG_COMPILE='vlog -work work +define+BRC_SIMU_ON'}
SCRIPT_DIR=`dirname $0`

# Compile VLOG. This is a complete list covering all configurations. Some will not be
# used, however it is usually most convenient to compile all of them, especially if the
# tools require components to be defined even when they are switched out with generate
# statements.

# When introducing your own RAM versions it is suggested to place these in a sub-directory
# 'decRams' that includes your RAMs and modified versions of the BRC wrappers.

cd $SCRIPT_DIR

$COMPILE_VLOG ldpcDecGlobal.v
# Behavioural RAM models
$COMPILE_VLOG ldpcDecSpRam.v ldpcDecDpRam.v ldpcDecTrueDpRam.v ldpcDecDpWeRam.v
# More RAMs
$COMPILE_VLOG  ldpcDecDpWrFirstRam.v ldpcDecDpWeWrFirstRam.v
# Wrappers around RAMs
$COMPILE_VLOG ldpcDecCellRam.v ldpcDecVrRam.v ldpcDecCrRam.v ldpcDecVmRam.v ldpcDecHdRam.v
# Your modified versions of the wrappers (uncomment when ready)
#$COMPILE_VLOG decRams/ldpcDecCellRam.v decRams/ldpcDecVrRam.v decRams/ldpcDecCrRam.v decRams/ldpcDecVmRam.v decRams/ldpcDecHdRam.v
# Additional wrappers for USE_CELL_ROM=1 and  NUM_PORTS=1 option
$COMPILE_VLOG ldpcDecCellRom.v ldpcDecVr1pRam.v ldpcDecCr1pRam.v
# Check/Variable response FIFOs - bothe single and dual port versions (selected with NUM_PORTS)
$COMPILE_VLOG  ldpcDecCrFifo1p.v ldpcDecCrFifo.v ldpcDecVrFifo1p.v ldpcDecVrFifo.v 
# Controller for VmMem
$COMPILE_VLOG ldpcDecHdRamMux.v ldpcDecVmRamMux.v ldpcDecVmMem.v 
# Main functional blocks
$COMPILE_VLOG ldpcDecOp.v ldpcDecIpPre.v ldpcDecIp.v ldpcDecCtrl.v 
$COMPILE_VLOG ldpcDecCM.v ldpcDecShort.v ldpcDecFwd.v ldpcDecBwdLog.v ldpcDecBwd.v
# Top level blocks
$COMPILE_VLOG ldpcDecRegs.v ldpcDecLookup.v ldpcDecCore.v ldpcDecClkGate.v ldpcDec.v

echo ""
echo "** ldpcDec RTL compile completed without errors"
echo ""


