lint_rtl
    This goal checks;
    - Basic connectivity issues in the design, such as floating input, width mismatch, etc. 
    - Simulation issues such as incomplete sensitivity list, incorrect use of blocking/non-blocking 
      assignments, potential functional errors possible simulation hang cases, and simulation race cases
    - Structural issues in the design that affect the post-implementation functionality or 
      performance of the design. Examples include multiple drivers, high fan-in mux, and 
      synchronous/asynchronous use of resets.
    - Synthesizable constructs in the design and code which can cause RTL vs. gate simulation mismatch. 

    Ideally this goal should be run before checking in new RTL changes.

design_audit (Optional)
    This goal provides design audit information. The aim of this goal is to gather statistics 
    of the design. These may include information on the Top level design, Black/Gray Boxes, 
    Parameters/Generics etc, and information on the design size, control signals etc.

clock_reset_integrity
The aim of this goal is to check the integrity of clock and reset architecture in the design. 
Such as the following;
    *   Possible race condition between clock and enable of FFs
    *   Complex Issues like Gated Clock or deep ripple clock divider

