power_verif_rtl

This goal checks the multiple voltage domain design for electrical correctness before synthesis. To check that the power intent has been applied correctly, look at the LP_DECOMPILE_CONSTRAINTS report first. The two key rules are LPSVM04 for level shifters, and LPSVM08 for isolation logic. Review the LPSVM08 violations before reviewing LPSVM09; many errors will generate one message for each rule.