00001
00011 #ifndef _DBG_H_
00012 #define _DBG_H_
00013
00014
00015
00016
00017
00018 #include "co_int.h"
00019 #include "rwnx_config.h"
00020 #include "compiler.h"
00021 #include "co_math.h"
00022 #include "reg_mac_pl.h"
00023 #include "reg_sysctrl.h"
00024 #include "dbg_profiling.h"
00025 #include "la.h"
00026 #include "la_mem.h"
00027 #include "phy.h"
00028 #include "trace.h"
00029 #include <stdarg.h>
00030
00049
00050
00051
00052
00053
00059
00060 #define NX_PRINT_NONE 0
00061 #define NX_PRINT_IPC 1
00062 #define NX_PRINT_PRINTF 2
00063 #define NX_PRINT_PRINTK 3
00064
00065
00066
00067 #define D_KE "\x80"
00068 #define D_DBG "\x81"
00069 #define D_IPC "\x82"
00070 #define D_DMA "\x83"
00071 #define D_MM "\x84"
00072 #define D_TX "\x85"
00073 #define D_RX "\x86"
00074 #define D_PHY "\x87"
00075 #define D_XX0 "\x88"
00076 #define D_XX1 "\x89"
00077 #define D_XX2 "\x8A"
00078 #define D_XX3 "\x8B"
00079 #define D_XX4 "\x8C"
00080
00081
00082
00083 #define D_CRT "\x9A"
00084 #define D_ERR "\x9B"
00085 #define D_WRN "\x9C"
00086 #define D_INF "\x9D"
00087 #define D_VRB "\x9E"
00088
00090 enum dbg_mod_tag
00091 {
00092 DBG_MOD_IDX_KE = 0,
00093 DBG_MOD_IDX_DBG,
00094 DBG_MOD_IDX_IPC,
00095 DBG_MOD_IDX_DMA,
00096 DBG_MOD_IDX_MM,
00097 DBG_MOD_IDX_TX,
00098 DBG_MOD_IDX_RX,
00099 DBG_MOD_IDX_PHY,
00100 DBG_MOD_IDX_MAX,
00101 };
00102
00103 #define DBG_MOD_MIN 0x80
00104 #define DBG_MOD_MAX (DBG_MOD_MIN + DBG_MOD_IDX_MAX)
00105
00106 #define DBG_MOD_ALL 0xFFFFFFFF
00107
00108
00110 enum dbg_sev_tag
00111 {
00112 DBG_SEV_IDX_NONE = 0,
00113 DBG_SEV_IDX_CRT,
00114 DBG_SEV_IDX_ERR,
00115 DBG_SEV_IDX_WRN,
00116 DBG_SEV_IDX_INF,
00117 DBG_SEV_IDX_VRB,
00118 DBG_SEV_IDX_MAX,
00119 DBG_SEV_ALL
00120 };
00121
00122 #define DBG_SEV_MIN 0x9A
00123 #define DBG_SEV_MAX 0xA0
00124
00125
00126 #if NX_PRINT != NX_PRINT_NONE
00127 void dbg_test_print(const char *fmt, ...);
00128 #define dbg(fmt, ...) dbg_test_print(fmt, ## __VA_ARGS__)
00129
00130 #else
00131 #define dbg(fmt, ...) do {} while (0)
00132 #endif
00133
00134 uint32_t dbg_snprintf(char *buffer, uint32_t size, const char *fmt, ...);
00135 uint32_t dbg_vsnprintf_offset(char *buffer, uint32_t size, uint32_t offset, const char *fmt, va_list args);
00136
00154 #define dbg_vsnprintf(buffer, size, fmt, args) dbg_vsnprintf_offset(buffer, size, 0, fmt, args)
00155
00156
00159
00160
00168
00169 #ifdef TX_IPC_IRQ_DEF
00170 #define PROF_TX_IPC_IRQ_SET() nxmac_sw_set_profiling_set(CO_BIT(TX_IPC_IRQ))
00171 #define PROF_TX_IPC_IRQ_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(TX_IPC_IRQ))
00172 #else
00173 #define PROF_TX_IPC_IRQ_SET()
00174 #define PROF_TX_IPC_IRQ_CLR()
00175 #endif
00176
00177 #ifdef TX_MACIF_EVT_DEF
00178 #define PROF_TX_MACIF_EVT_SET() nxmac_sw_set_profiling_set(CO_BIT(TX_MACIF_EVT))
00179 #define PROF_TX_MACIF_EVT_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(TX_MACIF_EVT))
00180 #else
00181 #define PROF_TX_MACIF_EVT_SET()
00182 #define PROF_TX_MACIF_EVT_CLR()
00183 #endif
00184
00185 #ifdef TX_DMA_IRQ_DEF
00186 #define PROF_TX_DMA_IRQ_SET() nxmac_sw_set_profiling_set(CO_BIT(TX_DMA_IRQ))
00187 #define PROF_TX_DMA_IRQ_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(TX_DMA_IRQ))
00188 #else
00189 #define PROF_TX_DMA_IRQ_SET()
00190 #define PROF_TX_DMA_IRQ_CLR()
00191 #endif
00192
00193 #ifdef TX_NEW_TAIL_DEF
00194 #define PROF_TX_NEW_TAIL_SET() nxmac_sw_set_profiling_set(CO_BIT(TX_NEW_TAIL))
00195 #define PROF_TX_NEW_TAIL_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(TX_NEW_TAIL))
00196 #else
00197 #define PROF_TX_NEW_TAIL_SET()
00198 #define PROF_TX_NEW_TAIL_CLR()
00199 #endif
00200
00201 #ifdef AGG_FIRST_MPDU_DWNLD_DEF
00202 #define PROF_AGG_FIRST_MPDU_DWNLD_SET() nxmac_sw_set_profiling_set(CO_BIT(AGG_FIRST_MPDU_DWNLD))
00203 #define PROF_AGG_FIRST_MPDU_DWNLD_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(AGG_FIRST_MPDU_DWNLD))
00204 #else
00205 #define PROF_AGG_FIRST_MPDU_DWNLD_SET()
00206 #define PROF_AGG_FIRST_MPDU_DWNLD_CLR()
00207 #endif
00208
00209 #ifdef AGG_START_AMPDU_DEF
00210 #define PROF_AGG_START_AMPDU_SET() nxmac_sw_set_profiling_set(CO_BIT(AGG_START_AMPDU))
00211 #define PROF_AGG_START_AMPDU_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(AGG_START_AMPDU))
00212 #else
00213 #define PROF_AGG_START_AMPDU_SET()
00214 #define PROF_AGG_START_AMPDU_CLR()
00215 #endif
00216
00217 #ifdef AGG_ADD_MPDU_DEF
00218 #define PROF_AGG_ADD_MPDU_SET() nxmac_sw_set_profiling_set(CO_BIT(AGG_ADD_MPDU))
00219 #define PROF_AGG_ADD_MPDU_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(AGG_ADD_MPDU))
00220 #else
00221 #define PROF_AGG_ADD_MPDU_SET()
00222 #define PROF_AGG_ADD_MPDU_CLR()
00223 #endif
00224
00225 #ifdef AGG_FINISH_AMPDU_DEF
00226 #define PROF_AGG_FINISH_AMPDU_SET() nxmac_sw_set_profiling_set(CO_BIT(AGG_FINISH_AMPDU))
00227 #define PROF_AGG_FINISH_AMPDU_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(AGG_FINISH_AMPDU))
00228 #else
00229 #define PROF_AGG_FINISH_AMPDU_SET()
00230 #define PROF_AGG_FINISH_AMPDU_CLR()
00231 #endif
00232
00233 #ifdef AGG_SMPDU_DONETX_DEF
00234 #define PROF_AGG_SMPDU_DONETX_SET() nxmac_sw_set_profiling_set(CO_BIT(AGG_SMPDU_DONETX))
00235 #define PROF_AGG_SMPDU_DONETX_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(AGG_SMPDU_DONETX))
00236 #else
00237 #define PROF_AGG_SMPDU_DONETX_SET()
00238 #define PROF_AGG_SMPDU_DONETX_CLR()
00239 #endif
00240
00241 #ifdef AGG_BAR_DONETX_DEF
00242 #define PROF_AGG_BAR_DONETX_SET() nxmac_sw_set_profiling_set(CO_BIT(AGG_BAR_DONETX))
00243 #define PROF_AGG_BAR_DONETX_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(AGG_BAR_DONETX))
00244 #else
00245 #define PROF_AGG_BAR_DONETX_SET()
00246 #define PROF_AGG_BAR_DONETX_CLR()
00247 #endif
00248
00249 #ifdef AGG_BA_RXED_DEF
00250 #define PROF_AGG_BA_RXED_SET() nxmac_sw_set_profiling_set(CO_BIT(AGG_BA_RXED))
00251 #define PROF_AGG_BA_RXED_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(AGG_BA_RXED))
00252 #else
00253 #define PROF_AGG_BA_RXED_SET()
00254 #define PROF_AGG_BA_RXED_CLR()
00255 #endif
00256
00257 #ifdef CHAN_CTXT_CDE_EVT_PROF_DEF
00258 #define PROF_CHAN_CTXT_CDE_EVT_SET() nxmac_sw_set_profiling_set(CO_BIT(CHAN_CTXT_CDE_EVT))
00259 #define PROF_CHAN_CTXT_CDE_EVT_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(CHAN_CTXT_CDE_EVT))
00260 #else
00261 #define PROF_CHAN_CTXT_CDE_EVT_SET()
00262 #define PROF_CHAN_CTXT_CDE_EVT_CLR()
00263 #endif
00264
00265 #ifdef CHAN_CTXT_TBTT_SWITCH_PROF_DEF
00266 #define PROF_CHAN_CTXT_TBTT_SWITCH_SET() nxmac_sw_set_profiling_set(CO_BIT(CHAN_CTXT_TBTT_SWITCH))
00267 #define PROF_CHAN_CTXT_TBTT_SWITCH_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(CHAN_CTXT_TBTT_SWITCH))
00268 #else
00269 #define PROF_CHAN_CTXT_TBTT_SWITCH_SET()
00270 #define PROF_CHAN_CTXT_TBTT_SWITCH_CLR()
00271 #endif
00272
00273 #ifdef CHAN_CTXT_TX_DISCARD_PROF_DEF
00274 #define PROF_CHAN_CTXT_TX_DISCARD_SET() nxmac_sw_set_profiling_set(CO_BIT(CHAN_CTXT_TX_DISCARD))
00275 #define PROF_CHAN_CTXT_TX_DISCARD_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(CHAN_CTXT_TX_DISCARD))
00276 #else
00277 #define PROF_CHAN_CTXT_TX_DISCARD_SET()
00278 #define PROF_CHAN_CTXT_TX_DISCARD_CLR()
00279 #endif
00280
00283 #ifdef CHAN_CTXT_IDX_PROF_DEF
00284 #define PROF_CHAN_CTXT_IDX_SET(idx) \
00285 { \
00286 uint32_t prof = nxmac_sw_profiling_get() & ~(0x7 << CHAN_CTXT_IDX_PROF); \
00287 nxmac_sw_profiling_set(prof | ((idx & 0x7) << CHAN_CTXT_IDX_PROF)); \
00288 }
00289 #else
00290 #define PROF_CHAN_CTXT_IDX_SET(idx)
00291 #endif
00292
00293 #ifdef CHAN_CTXT_WAIT_END_PROF_DEF
00294 #define PROF_CHAN_CTXT_WAIT_END_SET() nxmac_sw_set_profiling_set(CO_BIT(CHAN_CTXT_WAIT_END))
00295 #define PROF_CHAN_CTXT_WAIT_END_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(CHAN_CTXT_WAIT_END))
00296 #else
00297 #define PROF_CHAN_CTXT_WAIT_END_SET()
00298 #define PROF_CHAN_CTXT_WAIT_END_CLR()
00299 #endif
00300
00301 #ifdef CHAN_CTXT_SWITCH_PROF_DEF
00302 #define PROF_CHAN_CTXT_SWITCH_SET() nxmac_sw_set_profiling_set(CO_BIT(CHAN_CTXT_SWITCH))
00303 #define PROF_CHAN_CTXT_SWITCH_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(CHAN_CTXT_SWITCH))
00304 #else
00305 #define PROF_CHAN_CTXT_SWITCH_SET()
00306 #define PROF_CHAN_CTXT_SWITCH_CLR()
00307 #endif
00308
00309 #ifdef CHAN_CTXT_TBTT_PRES_PROF_DEF
00310 #define PROF_CHAN_CTXT_TBTT_PRES_SET() nxmac_sw_set_profiling_set(CO_BIT(CHAN_CTXT_TBTT_PRES))
00311 #define PROF_CHAN_CTXT_TBTT_PRES_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(CHAN_CTXT_TBTT_PRES))
00312 #else
00313 #define PROF_CHAN_CTXT_TBTT_PRES_SET()
00314 #define PROF_CHAN_CTXT_TBTT_PRES_CLR()
00315 #endif
00316
00317 #ifdef P2P_NOA_ABS_DEF
00318 #define PROF_P2P_NOA_ABS_SET(inst) nxmac_sw_set_profiling_set(CO_BIT(P2P_NOA_0_ABS + inst))
00319 #define PROF_P2P_NOA_ABS_CLR(inst) nxmac_sw_clear_profiling_clear(CO_BIT(P2P_NOA_0_ABS + inst))
00320 #else
00321 #define PROF_P2P_NOA_ABS_SET(inst)
00322 #define PROF_P2P_NOA_ABS_CLR(inst)
00323 #endif
00324 #ifdef P2P_CTW_DEF
00325 #define PROF_P2P_CTW_SET() nxmac_sw_set_profiling_set(CO_BIT(P2P_CTW))
00326 #define PROF_P2P_CTW_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(P2P_CTW))
00327 #else
00328 #define PROF_P2P_CTW_SET()
00329 #define PROF_P2P_CTW_CLR()
00330 #endif
00331 #ifdef P2P_WAIT_BCN_DEF
00332 #define PROF_P2P_WAIT_BCN_SET() nxmac_sw_set_profiling_set(CO_BIT(P2P_WAIT_BCN))
00333 #define PROF_P2P_WAIT_BCN_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(P2P_WAIT_BCN))
00334 #else
00335 #define PROF_P2P_WAIT_BCN_SET()
00336 #define PROF_P2P_WAIT_BCN_CLR()
00337 #endif
00338 #ifdef P2P_ABSENCE_DEF
00339 #define PROF_P2P_ABSENCE_SET() nxmac_sw_set_profiling_set(CO_BIT(P2P_ABSENCE))
00340 #define PROF_P2P_ABSENCE_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(P2P_ABSENCE))
00341 #else
00342 #define PROF_P2P_ABSENCE_SET()
00343 #define PROF_P2P_ABSENCE_CLR()
00344 #endif
00345 #ifdef P2P_PS_PAUSED_DEF
00346 #define PROF_P2P_PS_PAUSED_SET() nxmac_sw_set_profiling_set(CO_BIT(P2P_PS_PAUSED))
00347 #define PROF_P2P_PS_PAUSED_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(P2P_PS_PAUSED))
00348 #else
00349 #define PROF_P2P_PS_PAUSED_SET()
00350 #define PROF_P2P_PS_PAUSED_CLR()
00351 #endif
00352
00353 #ifdef MU_SEC_USER_IRQ_DEF
00354 #define PROF_MU_SEC_USER_IRQ_SET() nxmac_sw_set_profiling_set(CO_BIT(MU_SEC_USER_IRQ))
00355 #define PROF_MU_SEC_USER_IRQ_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(MU_SEC_USER_IRQ))
00356 #else
00357 #define PROF_MU_SEC_USER_IRQ_SET()
00358 #define PROF_MU_SEC_USER_IRQ_CLR()
00359 #endif
00360 #ifdef MU_PPDU_START_DEF
00361 #define PROF_MU_PPDU_START_SET() nxmac_sw_set_profiling_set(CO_BIT(MU_PPDU_START))
00362 #define PROF_MU_PPDU_START_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(MU_PPDU_START))
00363 #else
00364 #define PROF_MU_PPDU_START_SET()
00365 #define PROF_MU_PPDU_START_CLR()
00366 #endif
00367 #ifdef MU_MPDU_ADD_DEF
00368 #define PROF_MU_MPDU_ADD_SET() nxmac_sw_set_profiling_set(CO_BIT(MU_MPDU_ADD))
00369 #define PROF_MU_MPDU_ADD_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(MU_MPDU_ADD))
00370 #else
00371 #define PROF_MU_MPDU_ADD_SET()
00372 #define PROF_MU_MPDU_ADD_CLR()
00373 #endif
00374 #ifdef MU_PPDU_CLOSE_DEF
00375 #define PROF_MU_PPDU_CLOSE_SET() nxmac_sw_set_profiling_set(CO_BIT(MU_PPDU_CLOSE))
00376 #define PROF_MU_PPDU_CLOSE_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(MU_PPDU_CLOSE))
00377 #else
00378 #define PROF_MU_PPDU_CLOSE_SET()
00379 #define PROF_MU_PPDU_CLOSE_CLR()
00380 #endif
00383 #ifdef MU_USER_POS_DEF
00384 #define PROF_MU_USER_POS_SET(pos) \
00385 { \
00386 uint32_t prof = nxmac_sw_profiling_get() & ~(0x3 << MU_USER_POS); \
00387 nxmac_sw_profiling_set(prof | (((pos) & 0x3) << MU_USER_POS)); \
00388 }
00389 #else
00390 #define PROF_MU_USER_POS_SET(pos)
00391 #endif
00394 #ifdef MU_USER_POS_IRQ_DEF
00395 #define PROF_MU_USER_POS_IRQ_SET(idx) \
00396 { \
00397 uint32_t prof = nxmac_sw_profiling_get() & ~(0x3 << MU_USER_POS_IRQ); \
00398 nxmac_sw_profiling_set(prof | (((idx) & 0x3) << MU_USER_POS_IRQ)); \
00399 }
00400 #else
00401 #define PROF_MU_USER_POS_IRQ_SET(idx)
00402 #endif
00403
00404 #ifdef RADAR_IRQ_DEF
00405 #define PROF_RADAR_IRQ_SET() nxmac_sw_set_profiling_set(CO_BIT(RADAR_IRQ))
00406 #define PROF_RADAR_IRQ_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(RADAR_IRQ))
00407 #else
00408 #define PROF_RADAR_IRQ_SET()
00409 #define PROF_RADAR_IRQ_CLR()
00410 #endif
00411
00414 #ifdef TX_AC_BG_DEF
00415 #define PROF_TX_AC_BG_SET(ac) \
00416 { \
00417 uint32_t prof = nxmac_sw_profiling_get() & ~(0x3 << TX_AC_BG); \
00418 nxmac_sw_profiling_set(prof | (((ac) & 0x3) << TX_AC_BG)); \
00419 }
00420 #else
00421 #define PROF_TX_AC_BG_SET(ac)
00422 #endif
00423
00426 #ifdef TX_AC_IRQ_DEF
00427 #define PROF_TX_AC_IRQ_SET(ac) \
00428 { \
00429 uint32_t prof = nxmac_sw_profiling_get() & ~(0x3 << TX_AC_IRQ); \
00430 nxmac_sw_profiling_set(prof | (((ac) & 0x3) << TX_AC_IRQ)); \
00431 }
00432 #else
00433 #define PROF_TX_AC_IRQ_SET(ac)
00434 #endif
00435
00436 #ifdef TX_MAC_IRQ_DEF
00437 #define PROF_TX_MAC_IRQ_SET() nxmac_sw_set_profiling_set(CO_BIT(TX_MAC_IRQ))
00438 #define PROF_TX_MAC_IRQ_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(TX_MAC_IRQ))
00439 #else
00440 #define PROF_TX_MAC_IRQ_SET()
00441 #define PROF_TX_MAC_IRQ_CLR()
00442 #endif
00443
00444 #ifdef TX_HE_TRIG_IRQ_DEF
00445 #define PROF_TX_HE_TRIG_IRQ_SET() nxmac_sw_set_profiling_set(CO_BIT(TX_HE_TRIG_IRQ))
00446 #define PROF_TX_HE_TRIG_IRQ_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(TX_HE_TRIG_IRQ))
00447 #else
00448 #define PROF_TX_HE_TRIG_IRQ_SET()
00449 #define PROF_TX_HE_TRIG_IRQ_CLR()
00450 #endif
00451
00452 #ifdef TX_BUF_FREE_DEF
00453 #define PROF_TX_BUF_FREE_SET() nxmac_sw_set_profiling_set(CO_BIT(TX_BUF_FREE))
00454 #define PROF_TX_BUF_FREE_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(TX_BUF_FREE))
00455 #else
00456 #define PROF_TX_BUF_FREE_SET()
00457 #define PROF_TX_BUF_FREE_CLR()
00458 #endif
00459
00460 #ifdef TX_BUF_ALLOC_DEF
00461 #define PROF_TX_BUF_ALLOC_SET() nxmac_sw_set_profiling_set(CO_BIT(TX_BUF_ALLOC))
00462 #define PROF_TX_BUF_ALLOC_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(TX_BUF_ALLOC))
00463 #else
00464 #define PROF_TX_BUF_ALLOC_SET()
00465 #define PROF_TX_BUF_ALLOC_CLR()
00466 #endif
00467
00468 #ifdef TX_PAYL_HDL_DEF
00469 #define PROF_TX_PAYL_HDL_SET() nxmac_sw_set_profiling_set(CO_BIT(TX_PAYL_HDL))
00470 #define PROF_TX_PAYL_HDL_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(TX_PAYL_HDL))
00471 #else
00472 #define PROF_TX_PAYL_HDL_SET()
00473 #define PROF_TX_PAYL_HDL_CLR()
00474 #endif
00475
00476 #ifdef TX_CFM_EVT_DEF
00477 #define PROF_TX_CFM_EVT_SET() nxmac_sw_set_profiling_set(CO_BIT(TX_CFM_EVT))
00478 #define PROF_TX_CFM_EVT_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(TX_CFM_EVT))
00479 #else
00480 #define PROF_TX_CFM_EVT_SET()
00481 #define PROF_TX_CFM_EVT_CLR()
00482 #endif
00483
00484 #ifdef TX_CFM_DMA_IRQ_DEF
00485 #define PROF_TX_CFM_DMA_IRQ_SET() nxmac_sw_set_profiling_set(CO_BIT(TX_CFM_DMA_IRQ))
00486 #define PROF_TX_CFM_DMA_IRQ_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(TX_CFM_DMA_IRQ))
00487 #else
00488 #define PROF_TX_CFM_DMA_IRQ_SET()
00489 #define PROF_TX_CFM_DMA_IRQ_CLR()
00490 #endif
00491
00492 #ifdef MM_HW_IDLE_DEF
00493 #define PROF_MM_HW_IDLE_SET() nxmac_sw_set_profiling_set(CO_BIT(MM_HW_IDLE))
00494 #define PROF_MM_HW_IDLE_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(MM_HW_IDLE))
00495 #else
00496 #define PROF_MM_HW_IDLE_SET()
00497 #define PROF_MM_HW_IDLE_CLR()
00498 #endif
00499
00500 #ifdef MM_SET_CHANNEL_DEF
00501 #define PROF_MM_SET_CHANNEL_SET() nxmac_sw_set_profiling_set(CO_BIT(MM_SET_CHANNEL))
00502 #define PROF_MM_SET_CHANNEL_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(MM_SET_CHANNEL))
00503 #else
00504 #define PROF_MM_SET_CHANNEL_SET()
00505 #define PROF_MM_SET_CHANNEL_CLR()
00506 #endif
00507
00508 #ifdef TX_FRAME_PUSH_DEF
00509 #define PROF_TX_FRAME_PUSH_SET() nxmac_sw_set_profiling_set(CO_BIT(TX_FRAME_PUSH))
00510 #define PROF_TX_FRAME_PUSH_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(TX_FRAME_PUSH))
00511 #else
00512 #define PROF_TX_FRAME_PUSH_SET()
00513 #define PROF_TX_FRAME_PUSH_CLR()
00514 #endif
00515
00516 #ifdef TX_FRAME_CFM_DEF
00517 #define PROF_TX_FRAME_CFM_SET() nxmac_sw_set_profiling_set(CO_BIT(TX_FRAME_CFM))
00518 #define PROF_TX_FRAME_CFM_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(TX_FRAME_CFM))
00519 #else
00520 #define PROF_TX_FRAME_CFM_SET()
00521 #define PROF_TX_FRAME_CFM_CLR()
00522 #endif
00523
00524 #ifdef MSG_BASIC_PROF_DEF
00525 #define PROF_MSG_IRQ_SET() nxmac_sw_set_profiling_set(CO_BIT(MSG_IRQ))
00526 #define PROF_MSG_IRQ_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(MSG_IRQ))
00527 #define PROF_MSG_FWD_SET() nxmac_sw_set_profiling_set(CO_BIT(MSG_FWD))
00528 #define PROF_MSG_FWD_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(MSG_FWD))
00529 #define PROF_MSG_IPC_IND_SET() nxmac_sw_set_profiling_set(CO_BIT(MSG_IPC_IND))
00530 #define PROF_MSG_IPC_IND_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(MSG_IPC_IND))
00531 #else
00532 #define PROF_MSG_IRQ_SET()
00533 #define PROF_MSG_IRQ_CLR()
00534 #define PROF_MSG_FWD_SET()
00535 #define PROF_MSG_FWD_CLR()
00536 #define PROF_MSG_IPC_IND_SET()
00537 #define PROF_MSG_IPC_IND_CLR()
00538 #endif
00539
00540 #ifdef RX_MAC_IRQ_DEF
00541 #define PROF_RX_MAC_IRQ_SET() nxmac_sw_set_profiling_set(CO_BIT(RX_MAC_IRQ))
00542 #define PROF_RX_MAC_IRQ_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(RX_MAC_IRQ))
00543 #else
00544 #define PROF_RX_MAC_IRQ_SET()
00545 #define PROF_RX_MAC_IRQ_CLR()
00546 #endif
00547
00548 #ifdef RX_DMA_IRQ_DEF
00549 #define PROF_RX_DMA_IRQ_SET() nxmac_sw_set_profiling_set(CO_BIT(RX_DMA_IRQ))
00550 #define PROF_RX_DMA_IRQ_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(RX_DMA_IRQ))
00551 #else
00552 #define PROF_RX_DMA_IRQ_SET()
00553 #define PROF_RX_DMA_IRQ_CLR()
00554 #endif
00555
00556 #ifdef RX_DMA_EVT_DEF
00557 #define PROF_RX_DMA_EVT_SET() nxmac_sw_set_profiling_set(CO_BIT(RX_DMA_EVT))
00558 #define PROF_RX_DMA_EVT_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(RX_DMA_EVT))
00559 #else
00560 #define PROF_RX_DMA_EVT_SET()
00561 #define PROF_RX_DMA_EVT_CLR()
00562 #endif
00563
00564 #ifdef RX_IPC_IND_DEF
00565 #define PROF_RX_IPC_IND_SET() nxmac_sw_set_profiling_set(CO_BIT(RX_IPC_IND))
00566 #define PROF_RX_IPC_IND_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(RX_IPC_IND))
00567 #else
00568 #define PROF_RX_IPC_IND_SET()
00569 #define PROF_RX_IPC_IND_CLR()
00570 #endif
00571
00572 #ifdef RX_MPDU_XFER_DEF
00573 #define RX_MPDU_XFER_SET() nxmac_sw_set_profiling_set(CO_BIT(RX_MPDU_XFER))
00574 #define RX_MPDU_XFER_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(RX_MPDU_XFER))
00575 #else
00576 #define RX_MPDU_XFER_SET()
00577 #define RX_MPDU_XFER_CLR()
00578 #endif
00579
00580 #ifdef RX_MPDU_FREE_DEF
00581 #define RX_MPDU_FREE_SET() nxmac_sw_set_profiling_set(CO_BIT(RX_MPDU_FREE))
00582 #define RX_MPDU_FREE_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(RX_MPDU_FREE))
00583 #else
00584 #define RX_MPDU_FREE_SET()
00585 #define RX_MPDU_FREE_CLR()
00586 #endif
00587
00588 #ifdef RX_CNTRL_EVT_DEF
00589 #define RX_CNTRL_EVT_SET() nxmac_sw_set_profiling_set(CO_BIT(RX_CNTRL_EVT))
00590 #define RX_CNTRL_EVT_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(RX_CNTRL_EVT))
00591 #else
00592 #define RX_CNTRL_EVT_SET()
00593 #define RX_CNTRL_EVT_CLR()
00594 #endif
00595
00596 #ifdef RX_HOSTBUF_IDX_DEF
00597 #define RX_HOSTBUF_IDX_SET(val) nxmac_sw_set_profiling_set(val<<(RX_HOSTBUF_IDX))
00598 #define RX_HOSTBUF_IDX_CLR() nxmac_sw_clear_profiling_clear(0x0F<<(RX_HOSTBUF_IDX))
00599 #else
00600 #define RX_HOSTBUF_IDX_SET(val)
00601 #define RX_HOSTBUF_IDX_CLR()
00602 #endif
00603
00604 #ifdef HW_TBTT_EVT_DEF
00605 #define PROF_HW_TBTT_EVT_SET() nxmac_sw_set_profiling_set(CO_BIT(HW_TBTT_EVT))
00606 #define PROF_HW_TBTT_EVT_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(HW_TBTT_EVT))
00607 #else
00608 #define PROF_HW_TBTT_EVT_SET()
00609 #define PROF_HW_TBTT_EVT_CLR()
00610 #endif
00611
00612 #ifdef BCN_PRIM_TBTT_IRQ_DEF
00613 #define PROF_BCN_PRIM_TBTT_IRQ_SET() nxmac_sw_set_profiling_set(CO_BIT(BCN_PRIM_TBTT_IRQ))
00614 #define PROF_BCN_PRIM_TBTT_IRQ_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(BCN_PRIM_TBTT_IRQ))
00615 #else
00616 #define PROF_BCN_PRIM_TBTT_IRQ_SET()
00617 #define PROF_BCN_PRIM_TBTT_IRQ_CLR()
00618 #endif
00619
00620 #ifdef BCN_SEC_TBTT_IRQ_DEF
00621 #define PROF_BCN_SEC_TBTT_IRQ_SET() nxmac_sw_set_profiling_set(CO_BIT(BCN_SEC_TBTT_IRQ))
00622 #define PROF_BCN_SEC_TBTT_IRQ_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(BCN_SEC_TBTT_IRQ))
00623 #else
00624 #define PROF_BCN_SEC_TBTT_IRQ_SET()
00625 #define PROF_BCN_SEC_TBTT_IRQ_CLR()
00626 #endif
00627
00628 #ifdef AP_TBTT_DEF
00629 #define PROF_AP_TBTT_SET() nxmac_sw_set_profiling_set(CO_BIT(AP_TBTT))
00630 #define PROF_AP_TBTT_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(AP_TBTT))
00631 #else
00632 #define PROF_AP_TBTT_SET()
00633 #define PROF_AP_TBTT_CLR()
00634 #endif
00635
00636 #ifdef STA_TBTT_DEF
00637 #define PROF_STA_TBTT_SET() nxmac_sw_set_profiling_set(CO_BIT(STA_TBTT))
00638 #define PROF_STA_TBTT_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(STA_TBTT))
00639 #else
00640 #define PROF_STA_TBTT_SET()
00641 #define PROF_STA_TBTT_CLR()
00642 #endif
00643
00646 #ifdef TBTT_IDX_DEF
00647 #define PROF_TBTT_IDX_SET(idx) \
00648 { \
00649 uint32_t prof = nxmac_sw_profiling_get() & ~(0x7 << TBTT_IDX_PROF); \
00650 nxmac_sw_profiling_set(prof | ((idx & 0x7) << TBTT_IDX_PROF)); \
00651 }
00652 #else
00653 #define PROF_TBTT_IDX_SET(idx)
00654 #endif
00655
00656 #ifdef PS_SLEEP_DEF
00657 #define PROF_PS_SLEEP_SET() nxmac_sw_set_profiling_set(CO_BIT(PS_SLEEP))
00658 #define PROF_PS_SLEEP_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(PS_SLEEP))
00659 #else
00660 #define PROF_PS_SLEEP_SET()
00661 #define PROF_PS_SLEEP_CLR()
00662 #endif
00663
00664 #ifdef PS_PAUSE_DEF
00665 #define PROF_PS_PAUSE_SET() nxmac_sw_set_profiling_set(CO_BIT(PS_PAUSE))
00666 #define PROF_PS_PAUSE_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(PS_PAUSE))
00667 #else
00668 #define PROF_PS_PAUSE_SET()
00669 #define PROF_PS_PAUSE_CLR()
00670 #endif
00671
00672 #ifdef PS_DPSM_UPDATE_DEF
00673 #define PROF_PS_DPSM_UPDATE_SET() nxmac_sw_set_profiling_set(CO_BIT(PS_DPSM_UPDATE))
00674 #define PROF_PS_DPSM_UPDATE_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(PS_DPSM_UPDATE))
00675 #else
00676 #define PROF_PS_DPSM_UPDATE_SET()
00677 #define PROF_PS_DPSM_UPDATE_CLR()
00678 #endif
00679
00680 #ifdef PS_CHECK_RX_DEF
00681 #define PROF_PS_CHECK_RX_SET() nxmac_sw_set_profiling_set(CO_BIT(PS_CHECK_RX))
00682 #define PROF_PS_CHECK_RX_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(PS_CHECK_RX))
00683 #else
00684 #define PROF_PS_CHECK_RX_SET()
00685 #define PROF_PS_CHECK_RX_CLR()
00686 #endif
00687
00688 #ifdef PS_CHECK_TX_DEF
00689 #define PROF_PS_CHECK_TX_SET() nxmac_sw_set_profiling_set(CO_BIT(PS_CHECK_TX))
00690 #define PROF_PS_CHECK_TX_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(PS_CHECK_TX))
00691 #else
00692 #define PROF_PS_CHECK_TX_SET()
00693 #define PROF_PS_CHECK_TX_CLR()
00694 #endif
00695
00696 #ifdef PS_CHECK_BCN_DEF
00697 #define PROF_PS_CHECK_BCN_SET() nxmac_sw_set_profiling_set(CO_BIT(PS_CHECK_BCN))
00698 #define PROF_PS_CHECK_BCN_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(PS_CHECK_BCN))
00699 #else
00700 #define PROF_PS_CHECK_BCN_SET()
00701 #define PROF_PS_CHECK_BCN_CLR()
00702 #endif
00703
00704 #ifdef TD_CHECK_RX_DEF
00705 #define PROF_TD_CHECK_RX_SET() nxmac_sw_set_profiling_set(CO_BIT(TD_CHECK_RX))
00706 #define PROF_TD_CHECK_RX_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(TD_CHECK_RX))
00707 #else
00708 #define PROF_TD_CHECK_RX_SET()
00709 #define PROF_TD_CHECK_RX_CLR()
00710 #endif
00711
00712 #ifdef TD_CHECK_TX_DEF
00713 #define PROF_TD_CHECK_TX_SET() nxmac_sw_set_profiling_set(CO_BIT(TD_CHECK_TX))
00714 #define PROF_TD_CHECK_TX_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(TD_CHECK_TX))
00715 #else
00716 #define PROF_TD_CHECK_TX_SET()
00717 #define PROF_TD_CHECK_TX_CLR()
00718 #endif
00719
00720 #ifdef TD_CHECK_RX_PS_DEF
00721 #define PROF_TD_CHECK_RX_PS_SET() nxmac_sw_set_profiling_set(CO_BIT(TD_CHECK_RX_PS))
00722 #define PROF_TD_CHECK_RX_PS_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(TD_CHECK_RX_PS))
00723 #else
00724 #define PROF_TD_CHECK_RX_PS_SET()
00725 #define PROF_TD_CHECK_RX_PS_CLR()
00726 #endif
00727
00728 #ifdef TD_CHECK_TX_PS_DEF
00729 #define PROF_TD_CHECK_TX_PS_SET() nxmac_sw_set_profiling_set(CO_BIT(TD_CHECK_TX_PS))
00730 #define PROF_TD_CHECK_TX_PS_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(TD_CHECK_TX_PS))
00731 #else
00732 #define PROF_TD_CHECK_TX_PS_SET()
00733 #define PROF_TD_CHECK_TX_PS_CLR()
00734 #endif
00735
00736 #ifdef TD_TIMER_END_DEF
00737 #define PROF_TD_TIMER_END_SET() nxmac_sw_set_profiling_set(CO_BIT(TD_TIMER_END))
00738 #define PROF_TD_TIMER_END_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(TD_TIMER_END))
00739 #else
00740 #define PROF_TD_TIMER_END_SET()
00741 #define PROF_TD_TIMER_END_CLR()
00742 #endif
00743
00744 #ifdef BFR_MU_CALIB_DEF
00745 #define PROF_BFR_MU_CALIB_SET() nxmac_sw_set_profiling_set(CO_BIT(BFR_MU_CALIB))
00746 #define PROF_BFR_MU_CALIB_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(BFR_MU_CALIB))
00747 #else //(BFR_SU_CALIB_DEF)
00748 #define PROF_BFR_MU_CALIB_SET()
00749 #define PROF_BFR_MU_CALIB_CLR()
00750 #endif //(BFR_SU_CALIB_DEF)
00751
00752 #ifdef BFR_SU_CALIB_DEF
00753 #define PROF_BFR_SU_CALIB_SET() nxmac_sw_set_profiling_set(CO_BIT(BFR_SU_CALIB))
00754 #define PROF_BFR_SU_CALIB_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(BFR_SU_CALIB))
00755 #else //(BFR_SU_CALIB_DEF)
00756 #define PROF_BFR_SU_CALIB_SET()
00757 #define PROF_BFR_SU_CALIB_CLR()
00758 #endif //(BFR_SU_CALIB_DEF)
00759
00760 #ifdef BFR_RX_BFR_DEF
00761 #define PROF_BFR_RX_BFR_SET() nxmac_sw_set_profiling_set(CO_BIT(BFR_RX_BFR))
00762 #define PROF_BFR_RX_BFR_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(BFR_RX_BFR))
00763 #else //(BFR_RX_BFR_DEF)
00764 #define PROF_BFR_RX_BFR_SET()
00765 #define PROF_BFR_RX_BFR_CLR()
00766 #endif //(BFR_RX_BFR_DEF)
00767
00768 #ifdef BFR_UPLOAD_DEF
00769 #define PROF_BFR_UPLOAD_SET() nxmac_sw_set_profiling_set(CO_BIT(BFR_UPLOAD))
00770 #define PROF_BFR_UPLOAD_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(BFR_UPLOAD))
00771 #else //(BFR_UPLOAD_DEF)
00772 #define PROF_BFR_UPLOAD_SET()
00773 #define PROF_BFR_UPLOAD_CLR()
00774 #endif //(BFR_UPLOAD_DEF)
00775
00776 #ifdef BFR_DOWNLOAD_DEF
00777 #define PROF_BFR_DOWNLOAD_SET() nxmac_sw_set_profiling_set(CO_BIT(BFR_DOWNLOAD))
00778 #define PROF_BFR_DOWNLOAD_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(BFR_DOWNLOAD))
00779 #else //(BFR_DOWNLOAD_DEF)
00780 #define PROF_BFR_DOWNLOAD_SET()
00781 #define PROF_BFR_DOWNLOAD_CLR()
00782 #endif //(BFR_DOWNLOAD_DEF)
00783
00784 #ifdef BFR_TX_IND_DEF
00785 #define PROF_BFR_TX_IND_SET() nxmac_sw_set_profiling_set(CO_BIT(BFR_TX_IND))
00786 #define PROF_BFR_TX_IND_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(BFR_TX_IND))
00787 #else //(BFR_TX_IND_DEF)
00788 #define PROF_BFR_TX_IND_SET()
00789 #define PROF_BFR_TX_IND_CLR()
00790 #endif //(BFR_TX_IND_DEF)
00791
00792 #ifdef BFR_TX_CFM_DEF
00793 #define PROF_BFR_TX_CFM_SET() nxmac_sw_set_profiling_set(CO_BIT(BFR_TX_CFM))
00794 #define PROF_BFR_TX_CFM_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(BFR_TX_CFM))
00795 #else //(BFR_TX_CFM_DEF)
00796 #define PROF_BFR_TX_CFM_SET()
00797 #define PROF_BFR_TX_CFM_CLR()
00798 #endif //(BFR_TX_CFM_DEF)
00799
00802 #ifdef BFR_SMM_IDX_DEF
00803 #define PROF_SMM_IDX_SET(idx) \
00804 { \
00805 uint32_t prof = nxmac_sw_profiling_get() & ~(0xF << BFR_SMM_IDX_0); \
00806 nxmac_sw_profiling_set(prof | ((idx & 0xF) << BFR_SMM_IDX_0)); \
00807 }
00808 #else //(BFR_SMM_IDX_DEF)
00809 #define PROF_SMM_IDX_SET(idx)
00810 #endif //(BFR_SMM_IDX_DEF)
00811
00812 #ifdef RX_DUPLI_CHECK_DEF
00813 #define PROF_RX_DUPLI_CHECK_SET() nxmac_sw_set_profiling_set(CO_BIT(RX_DUPLI_CHECK))
00814 #define PROF_RX_DUPLI_CHECK_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(RX_DUPLI_CHECK))
00815 #else
00816 #define PROF_RX_DUPLI_CHECK_SET()
00817 #define PROF_RX_DUPLI_CHECK_CLR()
00818 #endif
00819
00820 #ifdef RX_DUPLI_NSTA_CHECK_DEF
00821 #define PROF_RX_DUPLI_NSTA_CHECK_SET() nxmac_sw_set_profiling_set(CO_BIT(RX_DUPLI_NSTA_CHECK))
00822 #define PROF_RX_DUPLI_NSTA_CHECK_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(RX_DUPLI_NSTA_CHECK))
00823 #else
00824 #define PROF_RX_DUPLI_NSTA_CHECK_SET()
00825 #define PROF_RX_DUPLI_NSTA_CHECK_CLR()
00826 #endif
00827
00828 #ifdef IPCDESC_PREPARE_DEF
00829 #define PROF_IPCDESC_PREPARE_SET() nxmac_sw_set_profiling_set(CO_BIT(IPCDESC_PREPARE))
00830 #define PROF_IPCDESC_PREPARE_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(IPCDESC_PREPARE))
00831 #else
00832 #define PROF_IPCDESC_PREPARE_SET()
00833 #define PROF_IPCDESC_PREPARE_CLR()
00834 #endif
00835
00836 #ifdef IPCDESC_TRANSFER_DEF
00837 #define PROF_IPCDESC_TRANSFER_SET() nxmac_sw_set_profiling_set(CO_BIT(IPCDESC_TRANSFER))
00838 #define PROF_IPCDESC_TRANSFER_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(IPCDESC_TRANSFER))
00839 #else
00840 #define PROF_IPCDESC_TRANSFER_SET()
00841 #define PROF_IPCDESC_TRANSFER_CLR()
00842 #endif
00843
00844 #ifdef DEFRAG_CHECK_DEF
00845 #define PROF_DEFRAG_CHECK_SET() nxmac_sw_set_profiling_set(CO_BIT(DEFRAG_CHECK))
00846 #define PROF_DEFRAG_CHECK_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(DEFRAG_CHECK))
00847 #else
00848 #define PROF_DEFRAG_CHECK_SET()
00849 #define PROF_DEFRAG_CHECK_CLR()
00850 #endif
00851
00852 #ifdef DEFRAG_TRANSFER_DEF
00853 #define PROF_DEFRAG_TRANSFER_SET() nxmac_sw_set_profiling_set(CO_BIT(DEFRAG_TRANSFER))
00854 #define PROF_DEFRAG_TRANSFER_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(DEFRAG_TRANSFER))
00855 #else
00856 #define PROF_DEFRAG_TRANSFER_SET()
00857 #define PROF_DEFRAG_TRANSFER_CLR()
00858 #endif
00859
00860 #ifdef DEFRAG_UPD_LENGTH_DEF
00861 #define PROF_DEFRAG_UPD_LENGTH_SET() nxmac_sw_set_profiling_set(CO_BIT(DEFRAG_UPD_LENGTH))
00862 #define PROF_DEFRAG_UPD_LENGTH_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(DEFRAG_UPD_LENGTH))
00863 #else
00864 #define PROF_DEFRAG_UPD_LENGTH_SET()
00865 #define PROF_DEFRAG_UPD_LENGTH_CLR()
00866 #endif
00867
00868 #ifdef REORD_CHECK_DEF
00869 #define PROF_REORD_CHECK_SET() nxmac_sw_set_profiling_set(CO_BIT(REORD_CHECK))
00870 #define PROF_REORD_CHECK_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(REORD_CHECK))
00871 #else
00872 #define PROF_REORD_CHECK_SET()
00873 #define PROF_REORD_CHECK_CLR()
00874 #endif
00875
00876 #ifdef REORD_BAR_CHECK_DEF
00877 #define PROF_REORD_BAR_CHECK_SET() nxmac_sw_set_profiling_set(CO_BIT(REORD_BAR_CHECK))
00878 #define PROF_REORD_BAR_CHECK_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(REORD_BAR_CHECK))
00879 #else
00880 #define PROF_REORD_BAR_CHECK_SET()
00881 #define PROF_REORD_BAR_CHECK_CLR()
00882 #endif
00883
00884 #ifdef REORD_FLUSH_DEF
00885 #define PROF_REORD_FLUSH_SET() nxmac_sw_set_profiling_set(CO_BIT(REORD_FLUSH))
00886 #define PROF_REORD_FLUSH_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(REORD_FLUSH))
00887 #else
00888 #define PROF_REORD_FLUSH_SET()
00889 #define PROF_REORD_FLUSH_CLR()
00890 #endif
00891
00892 #ifdef REORD_FWD_DEF
00893 #define PROF_REORD_FWD_SET() nxmac_sw_set_profiling_set(CO_BIT(REORD_FWD))
00894 #define PROF_REORD_FWD_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(REORD_FWD))
00895 #else
00896 #define PROF_REORD_FWD_SET()
00897 #define PROF_REORD_FWD_CLR()
00898 #endif
00899
00900 #ifdef MAC2ETH_UPDATE_DEF
00901 #define PROF_MAC2ETH_UPDATE_SET() nxmac_sw_set_profiling_set(CO_BIT(MAC2ETH_UPDATE))
00902 #define PROF_MAC2ETH_UPDATE_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(MAC2ETH_UPDATE))
00903 #else
00904 #define PROF_MAC2ETH_UPDATE_SET()
00905 #define PROF_MAC2ETH_UPDATE_CLR()
00906 #endif
00907
00908 #ifdef PS_PEER_STATE_DEF
00909 #define PROF_PS_PEER_STATE_SET() nxmac_sw_set_profiling_set(CO_BIT(PS_PEER_STATE))
00910 #define PROF_PS_PEER_STATE_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(PS_PEER_STATE))
00911 #else
00912 #define PROF_PS_PEER_STATE_SET()
00913 #define PROF_PS_PEER_STATE_CLR()
00914 #endif
00915
00916 #ifdef PS_BCMC_STATE_DEF
00917 #define PROF_PS_BCMC_STATE_SET() nxmac_sw_set_profiling_set(CO_BIT(PS_BCMC_STATE))
00918 #define PROF_PS_BCMC_STATE_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(PS_BCMC_STATE))
00919 #else
00920 #define PROF_PS_BCMC_STATE_SET()
00921 #define PROF_PS_BCMC_STATE_CLR()
00922 #endif
00923
00926 #ifdef PS_STATE_VAL_DEF
00927 #define PROF_PS_STATE_VAL_SET(val) \
00928 { \
00929 uint32_t prof = nxmac_sw_profiling_get() & ~(0x3 << PS_STATE_VAL); \
00930 nxmac_sw_profiling_set(prof | ((val & 0x3) << PS_STATE_VAL)); \
00931 }
00932 #else
00933 #define PROF_PS_STATE_VAL_SET(val)
00934 #endif
00935
00936 #ifdef PS_PSPOLL_RX_DEF
00937 #define PROF_PS_PSPOLL_RX_SET() nxmac_sw_set_profiling_set(CO_BIT(PS_PSPOLL_RX))
00938 #define PROF_PS_PSPOLL_RX_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(PS_PSPOLL_RX))
00939 #else
00940 #define PROF_PS_PSPOLL_RX_SET()
00941 #define PROF_PS_PSPOLL_RX_CLR()
00942 #endif
00943
00944 #ifdef PS_TRAFFIC_REQ_DEF
00945 #define PROF_PS_TRAFFIC_REQ_SET() nxmac_sw_set_profiling_set(CO_BIT(PS_TRAFFIC_REQ))
00946 #define PROF_PS_TRAFFIC_REQ_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(PS_TRAFFIC_REQ))
00947 #else
00948 #define PROF_PS_TRAFFIC_REQ_SET()
00949 #define PROF_PS_TRAFFIC_REQ_CLR()
00950 #endif
00951
00952 #ifdef BW_DROP_IRQ_DEF
00953 #define PROF_BW_DROP_IRQ_SET() nxmac_sw_set_profiling_set(CO_BIT(BW_DROP_IRQ))
00954 #define PROF_BW_DROP_IRQ_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(BW_DROP_IRQ))
00955 #else
00956 #define PROF_BW_DROP_IRQ_SET()
00957 #define PROF_BW_DROP_IRQ_CLR()
00958 #endif
00959
00960 #ifdef BW_DROP_STEP_DEF
00961 #define PROF_BW_DROP_STEP_SET() nxmac_sw_set_profiling_set(CO_BIT(BW_DROP_STEP))
00962 #define PROF_BW_DROP_STEP_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(BW_DROP_STEP))
00963 #else
00964 #define PROF_BW_DROP_STEP_SET()
00965 #define PROF_BW_DROP_STEP_CLR()
00966 #endif
00967
00968 #ifdef RC_UPD_COUNTERS_DEF
00969 #define PROF_RC_UPD_COUNTERS_SET() nxmac_sw_set_profiling_set(CO_BIT(RC_UPD_COUNTERS))
00970 #define PROF_RC_UPD_COUNTERS_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(RC_UPD_COUNTERS))
00971 #else
00972 #define PROF_RC_UPD_COUNTERS_SET()
00973 #define PROF_RC_UPD_COUNTERS_CLR()
00974 #endif
00975
00976 #ifdef RC_UPD_COUNTERS_TRIAL_DEF
00977 #define PROF_RC_UPD_COUNTERS_TRIAL_SET() nxmac_sw_set_profiling_set(CO_BIT(RC_UPD_COUNTERS_TRIAL))
00978 #define PROF_RC_UPD_COUNTERS_TRIAL_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(RC_UPD_COUNTERS_TRIAL))
00979 #else
00980 #define PROF_RC_UPD_COUNTERS_TRIAL_SET()
00981 #define PROF_RC_UPD_COUNTERS_TRIAL_CLR()
00982 #endif
00983
00984 #ifdef RC_STATS_CALC_DEF
00985 #define PROF_RC_STATS_CALC_SET() nxmac_sw_set_profiling_set(CO_BIT(RC_STATS_CALC))
00986 #define PROF_RC_STATS_CALC_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(RC_STATS_CALC))
00987 #else
00988 #define PROF_RC_STATS_CALC_SET()
00989 #define PROF_RC_STATS_CALC_CLR()
00990 #endif
00991
00992 #ifdef RC_UPD_RETRY_CHAIN_DEF
00993 #define PROF_RC_UPD_RETRY_CHAIN_SET() nxmac_sw_set_profiling_set(CO_BIT(RC_UPD_RETRY_CHAIN))
00994 #define PROF_RC_UPD_RETRY_CHAIN_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(RC_UPD_RETRY_CHAIN))
00995 #else
00996 #define PROF_RC_UPD_RETRY_CHAIN_SET()
00997 #define PROF_RC_UPD_RETRY_CHAIN_CLR()
00998 #endif
00999
01000 #ifdef RC_UPD_RETRY_CHAIN_TRIAL_DEF
01001 #define PROF_RC_UPD_RETRY_CHAIN_TRIAL_SET() nxmac_sw_set_profiling_set(CO_BIT(RC_UPD_RETRY_CHAIN_TRIAL))
01002 #define PROF_RC_UPD_RETRY_CHAIN_TRIAL_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(RC_UPD_RETRY_CHAIN_TRIAL))
01003 #else
01004 #define PROF_RC_UPD_RETRY_CHAIN_TRIAL_SET()
01005 #define PROF_RC_UPD_RETRY_CHAIN_TRIAL_CLR()
01006 #endif
01007
01008 #ifdef RC_SET_TRIAL_BUFFER_DEF
01009 #define PROF_RC_SET_TRIAL_BUFFER_SET() nxmac_sw_set_profiling_set(CO_BIT(RC_SET_TRIAL_BUFFER))
01010 #define PROF_RC_SET_TRIAL_BUFFER_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(RC_SET_TRIAL_BUFFER))
01011 #else
01012 #define PROF_RC_SET_TRIAL_BUFFER_SET()
01013 #define PROF_RC_SET_TRIAL_BUFFER_CLR()
01014 #endif
01015
01016 #ifdef RC_LOOKAROUND_TX_DEF
01017 #define PROF_RC_LOOKAROUND_TX_SET() nxmac_sw_set_profiling_set(CO_BIT(RC_LOOKAROUND_TX))
01018 #define PROF_RC_LOOKAROUND_TX_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(RC_LOOKAROUND_TX))
01019 #else
01020 #define PROF_RC_LOOKAROUND_TX_SET()
01021 #define PROF_RC_LOOKAROUND_TX_CLR()
01022 #endif
01023
01024 #ifdef RC_SW_RETRY_DEF
01025 #define PROF_RC_SW_RETRY_SET() nxmac_sw_set_profiling_set(CO_BIT(RC_SW_RETRY))
01026 #define PROF_RC_SW_RETRY_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(RC_SW_RETRY))
01027 #else
01028 #define PROF_RC_SW_RETRY_SET()
01029 #define PROF_RC_SW_RETRY_CLR()
01030 #endif
01031
01032 #ifdef FT_OVER_DS_REQ_DEF
01033 #define PROF_FT_OVER_DS_REQ_SET() nxmac_sw_set_profiling_set(CO_BIT(FT_OVER_DS_REQ))
01034 #define PROF_FT_OVER_DS_REQ_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(FT_OVER_DS_REQ))
01035 #else
01036 #define PROF_FT_OVER_DS_REQ_SET()
01037 #define PROF_FT_OVER_DS_REQ_CLR()
01038 #endif
01039
01040 #ifdef FT_REASSOC_DEF
01041 #define PROF_FT_REASSOC_SET() nxmac_sw_set_profiling_set(CO_BIT(FT_REASSOC))
01042 #define PROF_FT_REASSOC_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(FT_REASSOC))
01043 #else
01044 #define PROF_FT_REASSOC_SET()
01045 #define PROF_FT_REASSOC_CLR()
01046 #endif
01047
01048 #ifdef MESH_PS_ENABLE_DEF
01049 #define PROF_MESH_PS_ENABLE_SET() nxmac_sw_set_profiling_set(CO_BIT(MESH_PS_ENABLE))
01050 #define PROF_MESH_PS_ENABLE_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(MESH_PS_ENABLE))
01051 #else
01052 #define PROF_MESH_PS_ENABLE_SET()
01053 #define PROF_MESH_PS_ENABLE_CLR()
01054 #endif //(MESH_PS_ENABLE_DEF)
01055
01056 #ifdef MESH_PS_SP_OWNER_DEF
01057 #define PROF_MESH_PS_SP_OWNER_SET() nxmac_sw_set_profiling_set(CO_BIT(MESH_PS_SP_OWNER))
01058 #define PROF_MESH_PS_SP_OWNER_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(MESH_PS_SP_OWNER))
01059 #else
01060 #define PROF_MESH_PS_SP_OWNER_SET()
01061 #define PROF_MESH_PS_SP_OWNER_CLR()
01062 #endif //(MESH_PS_SP_OWNER_DEF)
01063
01064 #ifdef MESH_PS_SP_RECIP_DEF
01065 #define PROF_MESH_PS_SP_RECIP_SET() nxmac_sw_set_profiling_set(CO_BIT(MESH_PS_SP_RECIP))
01066 #define PROF_MESH_PS_SP_RECIP_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(MESH_PS_SP_RECIP))
01067 #else
01068 #define PROF_MESH_PS_SP_RECIP_SET()
01069 #define PROF_MESH_PS_SP_RECIP_CLR()
01070 #endif //(MESH_PS_SP_RECIP_DEF)
01071
01072 #ifdef MESH_PS_WAIT_BCMC_DEF
01073 #define PROF_MESH_PS_WAIT_BCMC_SET() nxmac_sw_set_profiling_set(CO_BIT(MESH_PS_WAIT_BCMC))
01074 #define PROF_MESH_PS_WAIT_BCMC_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(MESH_PS_WAIT_BCMC))
01075 #else
01076 #define PROF_MESH_PS_WAIT_BCMC_SET()
01077 #define PROF_MESH_PS_WAIT_BCMC_CLR()
01078 #endif //(MESH_PS_WAIT_BCMC_DEF)
01079
01080 #ifdef MESH_PS_WAIT_BCN_DEF
01081 #define PROF_MESH_PS_WAIT_BCN_SET() nxmac_sw_set_profiling_set(CO_BIT(MESH_PS_WAIT_BCN))
01082 #define PROF_MESH_PS_WAIT_BCN_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(MESH_PS_WAIT_BCN))
01083 #else
01084 #define PROF_MESH_PS_WAIT_BCN_SET()
01085 #define PROF_MESH_PS_WAIT_BCN_CLR()
01086 #endif //(MESH_PS_WAIT_BCN_DEF)
01087
01088 #ifdef MESH_PS_LOCAL_MAW_DEF
01089 #define PROF_MESH_PS_LOCAL_MAW_SET() nxmac_sw_set_profiling_set(CO_BIT(MESH_PS_LOCAL_MAW))
01090 #define PROF_MESH_PS_LOCAL_MAW_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(MESH_PS_LOCAL_MAW))
01091 #else
01092 #define PROF_MESH_PS_LOCAL_MAW_SET()
01093 #define PROF_MESH_PS_LOCAL_MAW_CLR()
01094 #endif //(MESH_PS_LOCAL_MAW_DEF)
01095
01096 #ifdef MESH_PS_PEER_MAW_DEF
01097 #define PROF_MESH_PS_PEER_MAW_SET() nxmac_sw_set_profiling_set(CO_BIT(MESH_PS_PEER_MAW))
01098 #define PROF_MESH_PS_PEER_MAW_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(MESH_PS_PEER_MAW))
01099 #else
01100 #define PROF_MESH_PS_PEER_MAW_SET()
01101 #define PROF_MESH_PS_PEER_MAW_CLR()
01102 #endif //(MESH_PS_PEER_MAW_DEF)
01103
01104 #ifdef CPU_SLEEP_DEF
01105 #define PROF_CPU_SLEEP_SET() nxmac_sw_set_profiling_set(CO_BIT(CPU_SLEEP))
01106 #define PROF_CPU_SLEEP_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(CPU_SLEEP))
01107 #else
01108 #define PROF_CPU_SLEEP_SET()
01109 #define PROF_CPU_SLEEP_CLR()
01110 #endif //CPU_SLEEP_DEF
01111
01112 #ifdef DEEP_SLEEP_DEF
01113 #define PROF_DEEP_SLEEP_SET() nxmac_sw_set_profiling_set(CO_BIT(DEEP_SLEEP))
01114 #define PROF_DEEP_SLEEP_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(DEEP_SLEEP))
01115 #else
01116 #define PROF_DEEP_SLEEP_SET()
01117 #define PROF_DEEP_SLEEP_CLR()
01118 #endif //DEEP_SLEEP_DEF
01119
01120 #ifdef TDLS_CHSW_REQ_RX_DEF
01121 #define PROF_TDLS_CHSW_REQ_RX_SET() nxmac_sw_set_profiling_set(CO_BIT(TDLS_RX_CHSW_REQ))
01122 #define PROF_TDLS_CHSW_REQ_RX_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(TDLS_RX_CHSW_REQ))
01123 #else
01124 #define PROF_TDLS_CHSW_REQ_RX_SET()
01125 #define PROF_TDLS_CHSW_REQ_RX_CLR()
01126 #endif
01127
01128 #ifdef TDLS_CHSW_RESP_RX_DEF
01129 #define PROF_TDLS_CHSW_RESP_RX_SET() nxmac_sw_set_profiling_set(CO_BIT(TDLS_RX_CHSW_RESP))
01130 #define PROF_TDLS_CHSW_RESP_RX_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(TDLS_RX_CHSW_RESP))
01131 #else
01132 #define PROF_TDLS_CHSW_RESP_RX_SET()
01133 #define PROF_TDLS_CHSW_RESP_RX_CLR()
01134 #endif
01135
01136 #ifdef TDLS_CHSW_REQ_TX_DEF
01137 #define PROF_TDLS_CHSW_REQ_TX_SET() nxmac_sw_set_profiling_set(CO_BIT(TDLS_TX_CHSW_REQ))
01138 #define PROF_TDLS_CHSW_REQ_TX_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(TDLS_TX_CHSW_REQ))
01139 #else
01140 #define PROF_TDLS_CHSW_REQ_TX_SET()
01141 #define PROF_TDLS_CHSW_REQ_TX_CLR()
01142 #endif
01143
01144 #ifdef TDLS_CHSW_RESP_TX_DEF
01145 #define PROF_TDLS_CHSW_RESP_TX_SET() nxmac_sw_set_profiling_set(CO_BIT(TDLS_TX_CHSW_RESP))
01146 #define PROF_TDLS_CHSW_RESP_TX_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(TDLS_TX_CHSW_RESP))
01147 #else
01148 #define PROF_TDLS_CHSW_RESP_TX_SET()
01149 #define PROF_TDLS_CHSW_RESP_TX_CLR()
01150 #endif
01151
01152 #ifdef TDLS_SWITCH_TO_OFFCH_DEF
01153 #define PROF_TDLS_SWITCH_TO_OFFCH_SET() nxmac_sw_set_profiling_set(CO_BIT(TDLS_SWITCH_TO_OFFCH))
01154 #define PROF_TDLS_SWITCH_TO_OFFCH_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(TDLS_SWITCH_TO_OFFCH))
01155 #else
01156 #define PROF_TDLS_SWITCH_TO_OFFCH_SET()
01157 #define PROF_TDLS_SWITCH_TO_OFFCH_CLR()
01158 #endif
01159
01160 #ifdef TDLS_SWITCH_TO_BASECH_DEF
01161 #define PROF_TDLS_SWITCH_TO_BASECH_SET() nxmac_sw_set_profiling_set(CO_BIT(TDLS_SWITCH_TO_BASECH))
01162 #define PROF_TDLS_SWITCH_TO_BASECH_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(TDLS_SWITCH_TO_BASECH))
01163 #else
01164 #define PROF_TDLS_SWITCH_TO_BASECH_SET()
01165 #define PROF_TDLS_SWITCH_TO_BASECH_CLR()
01166 #endif
01167
01168 #ifdef TDLS_CHSW_TIME_TIMER_DEF
01169 #define PROF_TDLS_CHSW_TIME_TIMER_SET() nxmac_sw_set_profiling_set(CO_BIT(TDLS_CHSW_TIME_TIMER))
01170 #define PROF_TDLS_CHSW_TIME_TIMER_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(TDLS_CHSW_TIME_TIMER))
01171 #else
01172 #define PROF_TDLS_CHSW_TIME_TIMER_SET()
01173 #define PROF_TDLS_CHSW_TIME_TIMER_CLR()
01174 #endif
01175
01176 #ifdef TDLS_CHSW_TIMEOUT_TIMER_DEF
01177 #define PROF_TDLS_CHSW_TIMEOUT_TIMER_SET() nxmac_sw_set_profiling_set(CO_BIT(TDLS_CHSW_TIMEOUT_TIMER))
01178 #define PROF_TDLS_CHSW_TIMEOUT_TIMER_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(TDLS_CHSW_TIMEOUT_TIMER))
01179 #else
01180 #define PROF_TDLS_CHSW_TIMEOUT_TIMER_SET()
01181 #define PROF_TDLS_CHSW_TIMEOUT_TIMER_CLR()
01182 #endif
01183
01184 #ifdef TDLS_CHSW_END_TIMER_DEF
01185 #define PROF_TDLS_CHSW_END_TIMER_SET() nxmac_sw_set_profiling_set(CO_BIT(TDLS_CHSW_END_TIMER))
01186 #define PROF_TDLS_CHSW_END_TIMER_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(TDLS_CHSW_END_TIMER))
01187 #else
01188 #define PROF_TDLS_CHSW_END_TIMER_SET()
01189 #define PROF_TDLS_CHSW_END_TIMER_CLR()
01190 #endif
01191
01192 #ifdef TDLS_CHSW_REQ_TX_TIMER_DEF
01193 #define PROF_TDLS_CHSW_REQ_TX_TIMER_SET() nxmac_sw_set_profiling_set(CO_BIT(TDLS_CHSW_REQ_TX_TIMER))
01194 #define PROF_TDLS_CHSW_REQ_TX_TIMER_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(TDLS_CHSW_REQ_TX_TIMER))
01195 #else
01196 #define PROF_TDLS_CHSW_REQ_TX_TIMER_SET()
01197 #define PROF_TDLS_CHSW_REQ_TX_TIMER_CLR()
01198 #endif
01199
01200 #ifdef TDLS_DELAY_CHSW_DEF
01201 #define PROF_TDLS_DELAY_CHSW_SET() nxmac_sw_set_profiling_set(CO_BIT(TDLS_DELAY_CHSW))
01202 #define PROF_TDLS_DELAY_CHSW_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(TDLS_DELAY_CHSW))
01203 #else
01204 #define PROF_TDLS_DELAY_CHSW_SET()
01205 #define PROF_TDLS_DELAY_CHSW_CLR()
01206 #endif
01207
01208 #ifdef TDLS_CHSW_NULL_FRAME_TX_DEF
01209 #define PROF_TDLS_CHSW_NULL_FRAME_TX_SET() nxmac_sw_set_profiling_set(CO_BIT(TDLS_TX_CHSW_NULL_FRAME))
01210 #define PROF_TDLS_CHSW_NULL_FRAME_TX_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(TDLS_TX_CHSW_NULL_FRAME))
01211 #else
01212 #define PROF_TDLS_CHSW_NULL_FRAME_TX_SET()
01213 #define PROF_TDLS_CHSW_NULL_FRAME_TX_CLR()
01214 #endif
01215
01218 #ifdef RTOS_TASK_DEF
01219 #define PROF_RTOS_TASK_SET(taskid) \
01220 { \
01221 uint32_t prof = nxmac_sw_profiling_get() & ~(0xF << RTOS_TASK); \
01222 nxmac_sw_profiling_set(prof | (((taskid) & 0xF) << RTOS_TASK)); \
01223 }
01224 #else
01225 #define PROF_RTOS_TASK_SET(taskid)
01226 #endif
01227
01228 #ifdef ANT_DIV_SWITCH_DEF
01229 #define PROF_ANT_DIV_SWITCH_SET() nxmac_sw_set_profiling_set(CO_BIT(ANT_DIV_SWITCH))
01230 #define PROF_ANT_DIV_SWITCH_CLR() nxmac_sw_clear_profiling_clear(CO_BIT(ANT_DIV_SWITCH))
01231 #else
01232 #define PROF_ANT_DIV_SWITCH_SET()
01233 #define PROF_ANT_DIV_SWITCH_CLR()
01234 #endif
01237
01239 enum
01240 {
01242 DBG_ERROR_RECOVERABLE = 0,
01244 DBG_ERROR_FATAL
01245 };
01246
01248 #define DBG_SW_DIAG_MAX_LEN 1024
01249
01251 #define DBG_ERROR_TRACE_SIZE 256
01252
01254 #define DBG_DIAGS_MAC_MAX 48
01255
01257 #define DBG_DIAGS_PHY_MAX 32
01258
01260 #define DBG_RHD_MEM_LEN (5 * 1024)
01261
01263 #define DBG_RBD_MEM_LEN (5 * 1024)
01264
01266 #define DBG_THD_MEM_LEN (10 * 1024)
01267
01269 struct dbg_debug_info_tag
01270 {
01272 uint32_t error_type;
01274 uint32_t rhd;
01276 uint32_t rhd_len;
01278 uint32_t rbd;
01280 uint32_t rbd_len;
01282 uint32_t thd[NX_TXQ_CNT];
01284 uint32_t thd_len[NX_TXQ_CNT];
01286 uint32_t hw_diag;
01288 uint32_t error[DBG_ERROR_TRACE_SIZE/4];
01290 uint32_t sw_diag_len;
01292 uint32_t sw_diag[DBG_SW_DIAG_MAX_LEN/4];
01294 struct phy_channel_info chan_info;
01296 struct la_conf_tag la_conf;
01298 uint16_t diags_mac[DBG_DIAGS_MAC_MAX];
01300 uint16_t diags_phy[DBG_DIAGS_PHY_MAX];
01302 uint32_t rhd_hw_ptr;
01304 uint32_t rbd_hw_ptr;
01305 };
01306
01308 struct dbg_debug_dump_tag
01309 {
01311 struct dbg_debug_info_tag dbg_info;
01312
01314 uint32_t rhd_mem[DBG_RHD_MEM_LEN/4];
01315
01317 uint32_t rbd_mem[DBG_RBD_MEM_LEN/4];
01318
01320 uint32_t thd_mem[NX_TXQ_CNT][DBG_THD_MEM_LEN/4];
01321
01323 uint32_t la_mem[sizeof(struct la_mem_format) * LA_MEM_LINE_COUNT / 4];
01324 };
01325
01326
01327 #if NX_SYS_STAT
01329 struct dbg_sys_stats_tag
01330 {
01332 uint32_t cpu_sleep_start;
01334 uint32_t cpu_sleep_time;
01336 uint32_t doze_start;
01338 uint32_t doze_time;
01340 uint32_t stats_time;
01342 uint32_t start_time;
01343 };
01344
01346 #define DBG_SYS_STAT_TIMEOUT (20 * 1000 * TU_DURATION)
01347 #endif
01348
01349
01350
01361 struct debug_env_tag
01362 {
01363 #if NX_PRINT == NX_PRINT_IPC
01364
01365
01366 #define DBG_PRINT_BUFFER_SIZE 256
01367 char print_buffer[DBG_PRINT_BUFFER_SIZE] __ALIGN4;
01368 uint8_t print_mutex;
01369 #endif
01371 char error[DBG_ERROR_TRACE_SIZE];
01373 uint32_t filter_module;
01375 uint32_t filter_severity;
01376 #if NX_SYS_STAT
01378 struct dbg_sys_stats_tag sys_stats;
01379 #endif
01380 };
01381
01383 extern struct debug_env_tag dbg_env;
01384
01390 #if NX_SYS_STAT
01391 __INLINE uint32_t dbg_sys_stats_time(void)
01392 {
01393 return sysctrl_timer_get();
01394 }
01395
01397 #define DBG_CPU_SLEEP_START() \
01398 { \
01399 dbg_env.sys_stats.cpu_sleep_start = dbg_sys_stats_time(); \
01400 PROF_CPU_SLEEP_SET(); \
01401 }
01402
01404 #define DBG_CPU_SLEEP_END() \
01405 { \
01406 uint32_t time; \
01407 PROF_CPU_SLEEP_CLR(); \
01408 time = dbg_sys_stats_time(); \
01409 dbg_env.sys_stats.cpu_sleep_time += (time - dbg_env.sys_stats.cpu_sleep_start) >> 10;\
01410 }
01411
01413 #define DBG_DOZE_START() \
01414 { \
01415 dbg_env.sys_stats.doze_start = dbg_sys_stats_time(); \
01416 PROF_DEEP_SLEEP_SET(); \
01417 }
01418
01420 #define DBG_DOZE_END() \
01421 { \
01422 uint32_t time; \
01423 PROF_DEEP_SLEEP_CLR(); \
01424 time = dbg_sys_stats_time(); \
01425 dbg_env.sys_stats.doze_time += (time - dbg_env.sys_stats.doze_start) >> 10; \
01426 }
01427 #else
01428 #define DBG_CPU_SLEEP_START() PROF_CPU_SLEEP_SET()
01429 #define DBG_CPU_SLEEP_END() PROF_CPU_SLEEP_CLR()
01430 #define DBG_DOZE_START() PROF_DEEP_SLEEP_SET()
01431 #define DBG_DOZE_END() PROF_DEEP_SLEEP_CLR()
01432 #endif
01433
01441 void dbg_init(void);
01442
01443 #if NX_DEBUG_DUMP
01444
01452 void dbg_error_ind(char *msg, uint32_t type);
01453
01462 void dbg_error_save(const char *error);
01463 #endif
01464
01465 #if NX_SYS_STAT
01466
01471 void dbg_sys_stat_reset(void);
01472 #endif
01473
01474
01476
01477 #endif // _DBG_H_
