Ceva-RW WLAN FullMAC SW documentation: /space/home/slher/rel/Beken/v6_4_5/macsw/modules/dbg/src/dbg

00001 
00011 #ifndef _DBG_PROFILING_H_
00012 #define _DBG_PROFILING_H_
00013 
00014 /*
00015  * INCLUDE FILES
00016  ****************************************************************************************
00017  */
00018 #include "rwnx_config.h"
00019 
00037 
00038 #if NX_PROFILING_ON
00039 #define TX_BASIC_PROF_DEF
00040 #define RX_BASIC_PROF_DEF
00041 #define MM_BASIC_PROF_DEF
00042 #define TX_AC_PROF_DEF
00043 //#define MSG_BASIC_PROF_DEF
00044 //#define SLEEP_PROF_DEF
00045 //#define TDLS_PROF_DEF
00046 //#define ANT_DIV_PROF_DEF
00047 #if NX_FULLY_HOSTED
00048 #define RTOS_TASK_DEF
00049 #define SLEEP_PROF_DEF
00050 #endif
00051 #if (NX_TX_FRAME)
00052 #define TX_FRAME_PROF_DEF
00053 #endif
00054 
00055 #if (NX_RADAR_DETECT)
00056 //#define RADAR_PROF_DEF
00057 #endif
00058 
00059 #if (NX_BEACONING || NX_POWERSAVE || NX_CONNECTION_MONITOR || NX_MULTI_ROLE)
00060 #define TBTT_PROF_DEF
00061 #endif
00062 
00063 #if (NX_AMPDU_TX)
00064 #define AGG_BASIC_PROF_DEF
00065 #endif
00066 
00067 #if (RW_MUMIMO_TX_EN)
00068 //#define MUMIMO_PROF_DEF
00069 #endif
00070 
00071 #if (NX_CHNL_CTXT)
00072 //#define CHNL_CTXT_PROF_DEF
00073 #endif //(NX_CHNL_CTXT)
00074 
00075 #if NX_MAC_HE
00076 #define TX_HE_PROF_DEF
00077 #endif // NX_MAC_HE
00078 
00079 #if (NX_P2P)
00080 //#define P2P_PROF_DEF
00081 #endif //(NX_P2P)
00082 
00083 #if (NX_DPSM)
00084 //#define DPSM_PROF_DEF
00085 #endif
00086 
00087 #if (NX_TD)
00088 //#define TD_PROF_DEF
00089 #endif //(NX_TD)
00090 
00091 #if (NX_BW_LEN_ADAPT)
00092 //#define BW_DROP_PROF_DEF
00093 #endif
00094 
00095 #if (RW_BFMER_EN)
00096 //#define BFR_PROF_DEF
00097 #endif //(RW_BFMER_EN)
00098 
00099 #if (NX_UMAC_PRESENT)
00100 //#define PS_PEER_PROF_DEF
00101 //#define DUPLI_PROF_DEF
00102 //#define IPCDESC_PROF_DEF
00103 //#define DEFRAG_PROF_DEF
00104 //#define RC_ALGO_PROF_DEF
00105 #if (NX_REORD)
00106 //#define REORD_PROF_DEF
00107 #endif
00108 
00109 #if (RW_UMESH_EN)
00110 //#define MESH_PS_PROF_DEF
00111 #endif //(RW_UMESH_EN)
00112 
00113 #endif
00114 
00115 #endif
00116 
00117 #ifdef SLEEP_PROF_DEF
00118 #define CPU_SLEEP_DEF
00119 #define DEEP_SLEEP_DEF
00120 #endif
00121 
00122 // Macros to enable/disable SW basic TX profiling bits individually
00123 #ifdef TX_BASIC_PROF_DEF
00124 #if !NX_FULLY_HOSTED
00125 #define TX_IPC_IRQ_DEF
00126 //#define TX_CFM_DMA_IRQ_DEF
00127 #define TX_BUF_ALLOC_DEF
00128 #define TX_DMA_IRQ_DEF
00129 #define TX_BUF_FREE_DEF
00130 #endif
00131 #define TX_MACIF_EVT_DEF
00132 #define TX_NEW_TAIL_DEF
00133 #define TX_MAC_IRQ_DEF
00134 #define TX_PAYL_HDL_DEF
00135 #define TX_CFM_EVT_DEF
00136 #endif
00137 
00138 // Macros to enable/disable access category profiling bits individually
00139 #ifdef TX_AC_PROF_DEF
00140 #define TX_AC_BG_DEF
00141 #define TX_AC_IRQ_DEF
00142 #endif
00143 
00144 // Macros to enable/disable TX HE profiling bits individually
00145 #ifdef TX_HE_PROF_DEF
00146 #define TX_HE_TRIG_IRQ_DEF
00147 #endif
00148 
00149 // Macros to enable/disable TX frame profiling bits individually
00150 #ifdef TX_FRAME_PROF_DEF
00151 #define TX_FRAME_PUSH_DEF
00152 #define TX_FRAME_CFM_DEF
00153 #endif
00154 
00155 // Macros to enable/disable SW basic RX profiling bits individually
00156 #ifdef RX_BASIC_PROF_DEF
00157 #define RX_MAC_IRQ_DEF
00158 #define RX_DMA_IRQ_DEF
00159 #define RX_DMA_EVT_DEF
00160 #define RX_MPDU_XFER_DEF
00161 #define RX_MPDU_FREE_DEF
00162 #define RX_CNTRL_EVT_DEF
00163 #if !NX_FULLY_HOSTED
00164 #define RX_IPC_IND_DEF
00165 #endif
00166 #endif
00167 
00168 #ifdef TBTT_PROF_DEF
00169 //#define HW_TBTT_EVT_DEF
00170 #if NX_POWERSAVE || NX_CONNECTION_MONITOR || NX_MULTI_ROLE
00171 #define STA_TBTT_DEF
00172 //#define AP_TBTT_DEF
00173 //#define TBTT_IDX_DEF
00174 #endif
00175 #endif
00176 
00177 #ifdef MM_BASIC_PROF_DEF
00178 #define MM_HW_IDLE_DEF
00179 #define MM_SET_CHANNEL_DEF
00180 #endif
00181 
00182 #ifdef DPSM_PROF_DEF
00183 #define PS_SLEEP_DEF
00184 #define PS_PAUSE_DEF
00185 #define PS_DPSM_UPDATE_DEF
00186 #define PS_CHECK_RX_DEF
00187 #define PS_CHECK_TX_DEF
00188 #define PS_CHECK_BCN_DEF
00189 #endif //(DPSM_PROF_DEF)
00190 
00191 #ifdef TD_PROF_DEF
00192 #define TD_CHECK_RX_DEF
00193 #define TD_CHECK_TX_DEF
00194 //#define TD_CHECK_RX_PS_DEF
00195 //#define TD_CHECK_TX_PS_DEF
00196 #define TD_TIMER_END_DEF
00197 #endif //(TD_PROF_DEF)
00198 
00199 #ifdef BFR_PROF_DEF
00200 #define BFR_SU_CALIB_DEF
00201 #define BFR_MU_CALIB_DEF
00202 #define BFR_RX_BFR_DEF
00203 #define BFR_UPLOAD_DEF
00204 #define BFR_DOWNLOAD_DEF
00205 #define BFR_TX_IND_DEF
00206 #define BFR_TX_CFM_DEF
00207 #define BFR_SMM_IDX_DEF
00208 #endif //(BFR_PROF_DEF)
00209 
00210 #ifdef DUPLI_PROF_DEF
00211 #define RX_DUPLI_CHECK_DEF
00212 #define RX_DUPLI_NSTA_CHECK_DEF
00213 #endif
00214 
00215 #ifdef IPCDESC_PROF_DEF
00216 #define IPCDESC_PREPARE_DEF
00217 #define IPCDESC_TRANSFER_DEF
00218 #endif
00219 
00220 #ifdef DEFRAG_PROF_DEF
00221 #define DEFRAG_CHECK_DEF
00222 #define DEFRAG_TRANSFER_DEF
00223 #define DEFRAG_UPD_LENGTH_DEF
00224 #endif
00225 
00226 #ifdef REORD_PROF_DEF
00227 #define REORD_CHECK_DEF
00228 #define REORD_BAR_CHECK_DEF
00229 #define REORD_FLUSH_DEF
00230 #define REORD_FWD_DEF
00231 #endif
00232 
00233 // Macros to enable/disable SW basic AGG profiling bits individually
00234 #ifdef AGG_BASIC_PROF_DEF
00235 #if !NX_FULLY_HOSTED
00236 #define AGG_FIRST_MPDU_DWNLD_DEF
00237 #endif
00238 #define AGG_START_AMPDU_DEF
00239 #define AGG_ADD_MPDU_DEF
00240 //#define AGG_SMPDU_DONETX_DEF
00241 #define AGG_FINISH_AMPDU_DEF
00242 #define AGG_BAR_DONETX_DEF
00243 #define AGG_BA_RXED_DEF
00244 #endif
00245 
00246 // Macros to enable/disable MUMIMO profiling bits individually
00247 #ifdef MUMIMO_PROF_DEF
00248 #define MU_SEC_USER_IRQ_DEF
00249 #define MU_PPDU_START_DEF
00250 #define MU_MPDU_ADD_DEF
00251 #define MU_PPDU_CLOSE_DEF
00252 #define MU_USER_POS_DEF
00253 #define MU_USER_POS_IRQ_DEF
00254 #endif
00255 
00256 #ifdef CHNL_CTXT_PROF_DEF
00257 #define CHAN_CTXT_CDE_EVT_PROF_DEF
00258 //#define CHAN_CTXT_TBTT_SWITCH_PROF_DEF
00259 #define CHAN_CTXT_IDX_PROF_DEF
00260 //#define CHAN_CTXT_TX_DISCARD_PROF_DEF
00261 #define CHAN_CTXT_WAIT_END_PROF_DEF
00262 //#define CHAN_CTXT_SWITCH_PROF_DEF
00263 #define CHAN_CTXT_TBTT_PRES_PROF_DEF
00264 #endif
00265 
00266 #ifdef P2P_PROF_DEF
00267 #define P2P_NOA_ABS_DEF
00268 #define P2P_CTW_DEF
00269 #define P2P_WAIT_BCN_DEF
00270 #define P2P_ABSENCE_DEF
00271 #define P2P_PS_PAUSED_DEF
00272 #endif
00273 
00274 #ifdef RADAR_PROF_DEF
00275 #define RADAR_IRQ_DEF
00276 #endif
00277 
00278 #ifdef PS_PEER_PROF_DEF
00279 #define PS_PEER_STATE_DEF
00280 #define PS_BCMC_STATE_DEF
00281 #define PS_STATE_VAL_DEF
00282 #define PS_PSPOLL_RX_DEF
00283 #define PS_TRAFFIC_REQ_DEF
00284 #endif //(PS_PEER_PROF_DEF)
00285 
00286 // Macros to enable/disable SW basic AGG profiling bits individually
00287 #ifdef BW_DROP_PROF_DEF
00288 #define BW_DROP_IRQ_DEF
00289 #define BW_DROP_STEP_DEF
00290 #endif
00291 
00292 // Macros to enable/disable rate control algorithm profiling bits individually
00293 #ifdef RC_ALGO_PROF_DEF
00294 #define RC_UPD_COUNTERS_DEF
00295 #define RC_UPD_COUNTERS_TRIAL_DEF
00296 #define RC_STATS_CALC_DEF
00297 #define RC_UPD_RETRY_CHAIN_DEF
00298 #define RC_UPD_RETRY_CHAIN_TRIAL_DEF
00299 #define RC_SET_TRIAL_BUFFER_DEF
00300 #define RC_LOOKAROUND_TX_DEF
00301 #define RC_SW_RETRY_DEF
00302 #endif
00303 
00304 #ifdef FT_PROF_DEF
00305 #define FT_OVER_DS_REQ_DEF
00306 #define FT_REASSOC_DEF
00307 #endif
00308 
00309 #ifdef MESH_PS_PROF_DEF
00310 #define MESH_PS_ENABLE_DEF
00311 #define MESH_PS_SP_OWNER_DEF
00312 #define MESH_PS_SP_RECIP_DEF
00313 #define MESH_PS_WAIT_BCMC_DEF
00314 #define MESH_PS_WAIT_BCN_DEF
00315 #define MESH_PS_LOCAL_MAW_DEF
00316 #define MESH_PS_PEER_MAW_DEF
00317 #endif //(MESH_PS_PROF_DEF)
00318 
00319 #ifdef TDLS_PROF_DEF
00320 //#define TDLS_CHSW_REQ_RX_DEF
00321 //#define TDLS_CHSW_RESP_TX_DEF
00322 //#define TDLS_CHSW_REQ_TX_DEF
00323 //#define TDLS_CHSW_RESP_RX_DEF
00324 #define TDLS_SWITCH_TO_OFFCH_DEF
00325 #define TDLS_SWITCH_TO_BASECH_DEF
00326 //#define TDLS_CHSW_TIME_TIMER_DEF
00327 //#define TDLS_CHSW_TIMEOUT_TIMER_DEF
00328 //#define TDLS_CHSW_REQ_TX_TIMER_DEF
00329 //#define TDLS_CHSW_END_TIMER_DEF
00330 #define TDLS_DELAY_CHSW_DEF
00331 #endif
00332 
00333 #ifdef ANT_DIV_PROF_DEF
00334 #define ANT_DIV_SWITCH_DEF
00335 #endif
00336 
00338 
00344 
00345 enum
00346 {
00347     #ifdef TX_IPC_IRQ_DEF
00348     TX_IPC_IRQ,
00349     #endif
00350     #ifdef TX_MACIF_EVT_DEF
00351     TX_MACIF_EVT,
00352     #endif
00353     #ifdef TX_BUF_ALLOC_DEF
00354     TX_BUF_ALLOC,
00355     #endif
00356     #ifdef TX_DMA_IRQ_DEF
00357     TX_DMA_IRQ,
00358     #endif
00359     #ifdef TX_PAYL_HDL_DEF
00360     TX_PAYL_HDL,
00361     #endif
00362     #ifdef TX_NEW_TAIL_DEF
00363     TX_NEW_TAIL,
00364     #endif
00365     #ifdef TX_MAC_IRQ_DEF
00366     TX_MAC_IRQ,
00367     #endif
00368     #ifdef TX_BUF_FREE_DEF
00369     TX_BUF_FREE,
00370     #endif
00371     #ifdef TX_CFM_EVT_DEF
00372     TX_CFM_EVT,
00373     #endif
00374     #ifdef TX_CFM_DMA_IRQ_DEF
00375     TX_CFM_DMA_IRQ,
00376     #endif
00377     #ifdef TX_HE_TRIG_IRQ_DEF
00378     TX_HE_TRIG_IRQ,
00379     #endif
00380     #ifdef MSG_BASIC_PROF_DEF
00381     MSG_IRQ,
00382     MSG_FWD,
00383     MSG_IPC_IND,
00384     #endif
00385     #ifdef RX_MAC_IRQ_DEF
00386     RX_MAC_IRQ,
00387     #endif
00388     #ifdef RX_CNTRL_EVT_DEF
00389     RX_CNTRL_EVT,
00390     #endif
00391     #ifdef RX_MPDU_XFER_DEF
00392     RX_MPDU_XFER,
00393     #endif
00394     #ifdef RX_MPDU_FREE_DEF
00395     RX_MPDU_FREE,
00396     #endif
00397     #ifdef RX_DMA_IRQ_DEF
00398     RX_DMA_IRQ,
00399     #endif
00400     #ifdef RX_DMA_EVT_DEF
00401     RX_DMA_EVT,
00402     #endif
00403     #ifdef RX_IPC_IND_DEF
00404     RX_IPC_IND,
00405     #endif
00406     #ifdef RX_HOSTBUF_IDX_DEF
00407     RX_HOSTBUF_IDX,
00408     #endif
00409     #ifdef AGG_FIRST_MPDU_DWNLD_DEF
00410     AGG_FIRST_MPDU_DWNLD,
00411     #endif
00412     #ifdef AGG_START_AMPDU_DEF
00413     AGG_START_AMPDU,
00414     #endif
00415     #ifdef AGG_ADD_MPDU_DEF
00416     AGG_ADD_MPDU,
00417     #endif
00418     #ifdef AGG_FINISH_AMPDU_DEF
00419     AGG_FINISH_AMPDU,
00420     #endif
00421     #ifdef AGG_SMPDU_DONETX_DEF
00422     AGG_SMPDU_DONETX,
00423     #endif
00424     #ifdef AGG_BAR_DONETX_DEF
00425     AGG_BAR_DONETX,
00426     #endif
00427     #ifdef AGG_BA_RXED_DEF
00428     AGG_BA_RXED,
00429     #endif
00430 
00431     #ifdef MU_SEC_USER_IRQ_DEF
00432     MU_SEC_USER_IRQ,
00433     #endif
00434     #ifdef MU_PPDU_START_DEF
00435     MU_PPDU_START,
00436     #endif
00437     #ifdef MU_MPDU_ADD_DEF
00438     MU_MPDU_ADD,
00439     #endif
00440     #ifdef MU_PPDU_CLOSE_DEF
00441     MU_PPDU_CLOSE,
00442     #endif
00443     #ifdef MU_USER_POS_DEF
00444     MU_USER_POS,
00445     MU_USER_POS_LAST,
00446     #endif
00447     #ifdef MU_USER_POS_IRQ_DEF
00448     MU_USER_POS_IRQ,
00449     MU_USER_POS_IRQ_LAST,
00450     #endif
00451 
00452     #ifdef CHAN_CTXT_CDE_EVT_PROF_DEF
00453     CHAN_CTXT_CDE_EVT,
00454     #endif
00455     #ifdef CHAN_CTXT_TBTT_SWITCH_PROF_DEF
00456     CHAN_CTXT_TBTT_SWITCH,
00457     #endif
00458     #ifdef CHAN_CTXT_IDX_PROF_DEF
00459     CHAN_CTXT_IDX_PROF,
00460     CHAN_CTXT_IDX_1    = CHAN_CTXT_IDX_PROF + 1,
00461     CHAN_CTXT_IDX_LAST = CHAN_CTXT_IDX_PROF + 2,
00462     #endif
00463     #ifdef CHAN_CTXT_TX_DISCARD_PROF_DEF
00464     CHAN_CTXT_TX_DISCARD,
00465     #endif
00466     #ifdef CHAN_CTXT_WAIT_END_PROF_DEF
00467     CHAN_CTXT_WAIT_END,
00468     #endif
00469     #ifdef CHAN_CTXT_SWITCH_PROF_DEF
00470     CHAN_CTXT_SWITCH,
00471     #endif
00472     #ifdef CHAN_CTXT_TBTT_PRES_PROF_DEF
00473     CHAN_CTXT_TBTT_PRES,
00474     #endif
00475 
00476     #ifdef P2P_NOA_ABS_DEF
00477     P2P_NOA_0_ABS,
00478     P2P_NOA_1_ABS,
00479     #endif
00480     #ifdef P2P_CTW_DEF
00481     P2P_CTW,
00482     #endif
00483     #ifdef P2P_WAIT_BCN_DEF
00484     P2P_WAIT_BCN,
00485     #endif
00486     #ifdef P2P_ABSENCE_DEF
00487     P2P_ABSENCE,
00488     #endif
00489     #ifdef P2P_PS_PAUSED_DEF
00490     P2P_PS_PAUSED,
00491     #endif
00492 
00493     #ifdef MM_HW_IDLE_DEF
00494     MM_HW_IDLE,
00495     #endif
00496     #ifdef MM_SET_CHANNEL_DEF
00497     MM_SET_CHANNEL,
00498     #endif
00499     #ifdef RADAR_IRQ_DEF
00500     RADAR_IRQ,
00501     #endif
00502     #ifdef TX_FRAME_PUSH_DEF
00503     TX_FRAME_PUSH,
00504     #endif
00505     #ifdef TX_FRAME_CFM_DEF
00506     TX_FRAME_CFM,
00507     #endif
00508     #ifdef TX_AC_BG_DEF
00509     TX_AC_BG,
00510     TX_AC_BG_LAST = TX_AC_BG + 1,
00511     #endif
00512     #ifdef TX_AC_IRQ_DEF
00513     TX_AC_IRQ,
00514     TX_AC_IRQ_LAST = TX_AC_IRQ + 1,
00515     #endif
00516     #ifdef BCN_PRIM_TBTT_IRQ_DEF
00517     BCN_PRIM_TBTT_IRQ,
00518     #endif
00519     #ifdef BCN_SEC_TBTT_IRQ_DEF
00520     BCN_SEC_TBTT_IRQ,
00521     #endif
00522     #ifdef HW_TBTT_EVT_DEF
00523     HW_TBTT_EVT,
00524     #endif
00525     #ifdef AP_TBTT_DEF
00526     AP_TBTT,
00527     #endif
00528     #ifdef STA_TBTT_DEF
00529     STA_TBTT,
00530     #endif
00531     #ifdef TBTT_IDX_DEF
00532     TBTT_IDX_PROF,
00533     TBTT_IDX_1    = TBTT_IDX_PROF + 1,
00534     TBTT_IDX_LAST = TBTT_IDX_PROF + 2,
00535     #endif
00536 
00537     #ifdef PS_SLEEP_DEF
00538     PS_SLEEP,
00539     #endif
00540     #ifdef PS_PAUSE_DEF
00541     PS_PAUSE,
00542     #endif
00543     #ifdef PS_DPSM_UPDATE_DEF
00544     PS_DPSM_UPDATE,
00545     #endif
00546     #ifdef PS_CHECK_RX_DEF
00547     PS_CHECK_RX,
00548     #endif
00549     #ifdef PS_CHECK_TX_DEF
00550     PS_CHECK_TX,
00551     #endif
00552     #ifdef PS_CHECK_BCN_DEF
00553     PS_CHECK_BCN,
00554     #endif
00555 
00556     #ifdef TD_CHECK_RX_DEF
00557     TD_CHECK_RX,
00558     #endif
00559     #ifdef TD_CHECK_TX_DEF
00560     TD_CHECK_TX,
00561     #endif
00562     #ifdef TD_CHECK_RX_PS_DEF
00563     TD_CHECK_RX_PS,
00564     #endif
00565     #ifdef TD_CHECK_TX_PS_DEF
00566     TD_CHECK_TX_PS,
00567     #endif
00568     #ifdef TD_TIMER_END_DEF
00569     TD_TIMER_END,
00570     #endif
00571 
00572     #ifdef BFR_MU_CALIB_DEF
00573     BFR_MU_CALIB,
00574     #endif //(BFR_MU_CALIB_DEF)
00575     #ifdef BFR_SU_CALIB_DEF
00576     BFR_SU_CALIB,
00577     #endif //(BFR_SU_CALIB_DEF)
00578     #ifdef BFR_RX_BFR_DEF
00579     BFR_RX_BFR,
00580     #endif //(BFR_RX_BFR_DEF)
00581     #ifdef BFR_UPLOAD_DEF
00582     BFR_UPLOAD,
00583     #endif //(BFR_UPLOAD_DEF)
00584     #ifdef BFR_DOWNLOAD_DEF
00585     BFR_DOWNLOAD,
00586     #endif //(BFR_DOWNLOAD_DEF)
00587     #ifdef BFR_TX_IND_DEF
00588     BFR_TX_IND,
00589     #endif //(BFR_TX_IND_DEF)
00590     #ifdef BFR_TX_CFM_DEF
00591     BFR_TX_CFM,
00592     #endif //(BFR_TX_CFM_DEF)
00593     #ifdef BFR_SMM_IDX_DEF
00594     BFR_SMM_IDX_0,
00595     BFR_SMM_IDX_1,
00596     BFR_SMM_IDX_2,
00597     BFR_SMM_IDX_LAST,
00598     #endif //(BFR_SMM_IDX_DEF)
00599 
00600     #ifdef RX_DUPLI_CHECK_DEF
00601     RX_DUPLI_CHECK,
00602     #endif
00603     #ifdef RX_DUPLI_NSTA_CHECK_DEF
00604     RX_DUPLI_NSTA_CHECK,
00605     #endif
00606 
00607     #ifdef IPCDESC_PREPARE_DEF
00608     IPCDESC_PREPARE,
00609     #endif
00610     #ifdef IPCDESC_TRANSFER_DEF
00611     IPCDESC_TRANSFER,
00612     #endif
00613 
00614     #ifdef DEFRAG_CHECK_DEF
00615     DEFRAG_CHECK,
00616     #endif
00617     #ifdef DEFRAG_TRANSFER_DEF
00618     DEFRAG_TRANSFER,
00619     #endif
00620     #ifdef DEFRAG_UPD_LENGTH_DEF
00621     DEFRAG_UPD_LENGTH,
00622     #endif
00623 
00624     #ifdef REORD_CHECK_DEF
00625     REORD_CHECK,
00626     #endif
00627     #ifdef REORD_BAR_CHECK_DEF
00628     REORD_BAR_CHECK,
00629     #endif
00630     #ifdef REORD_FLUSH_DEF
00631     REORD_FLUSH,
00632     #endif
00633     #ifdef REORD_FWD_DEF
00634     REORD_FWD,
00635     #endif
00636 
00637     #ifdef MAC2ETH_UPDATE_DEF
00638     MAC2ETH_UPDATE,
00639     #endif
00640 
00641     #ifdef PS_PEER_STATE_DEF
00642     PS_PEER_STATE,
00643     #endif
00644     #ifdef PS_BCMC_STATE_DEF
00645     PS_BCMC_STATE,
00646     #endif
00647     #ifdef PS_STATE_VAL_DEF
00648     PS_STATE_VAL,
00649     PS_STATE_VAL_LAST = PS_STATE_VAL + 1,
00650     #endif
00651     #ifdef PS_PSPOLL_RX_DEF
00652     PS_PSPOLL_RX,
00653     #endif
00654     #ifdef PS_TRAFFIC_REQ_DEF
00655     PS_TRAFFIC_REQ,
00656     #endif
00657     #ifdef BW_DROP_IRQ_DEF
00658     BW_DROP_IRQ,
00659     #endif
00660     #ifdef BW_DROP_STEP_DEF
00661     BW_DROP_STEP,
00662     #endif
00663 
00664     #ifdef RC_UPD_COUNTERS_DEF
00665     RC_UPD_COUNTERS,
00666     #endif
00667     #ifdef RC_UPD_COUNTERS_TRIAL_DEF
00668     RC_UPD_COUNTERS_TRIAL,
00669     #endif
00670     #ifdef RC_STATS_CALC_DEF
00671     RC_STATS_CALC,
00672     #endif
00673     #ifdef RC_UPD_RETRY_CHAIN_DEF
00674     RC_UPD_RETRY_CHAIN,
00675     #endif
00676     #ifdef RC_UPD_RETRY_CHAIN_TRIAL_DEF
00677     RC_UPD_RETRY_CHAIN_TRIAL,
00678     #endif
00679     #ifdef RC_LOOKAROUND_TX_DEF
00680     RC_LOOKAROUND_TX,
00681     #endif
00682     #ifdef RC_SET_TRIAL_BUFFER_DEF
00683     RC_SET_TRIAL_BUFFER,
00684     #endif
00685     #ifdef RC_SW_RETRY_DEF
00686     RC_SW_RETRY,
00687     #endif
00688 
00689     #ifdef FT_OVER_DS_REQ_DEF
00690     FT_OVER_DS_REQ,
00691     #endif
00692     #ifdef FT_REASSOC_DEF
00693     FT_REASSOC,
00694     #endif
00695 
00696     #ifdef MESH_PS_ENABLE_DEF
00697     MESH_PS_ENABLE,
00698     #endif //(MESH_PS_ENABLE_DEF)
00699     #ifdef MESH_PS_SP_OWNER_DEF
00700     MESH_PS_SP_OWNER,
00701     #endif //(MESH_PS_SP_OWNER_DEF)
00702     #ifdef MESH_PS_SP_RECIP_DEF
00703     MESH_PS_SP_RECIP,
00704     #endif //(MESH_PS_SP_RECIP_DEF)
00705     #ifdef MESH_PS_WAIT_BCMC_DEF
00706     MESH_PS_WAIT_BCMC,
00707     #endif //(MESH_PS_WAIT_BCMC_DEF)
00708     #ifdef MESH_PS_WAIT_BCN_DEF
00709     MESH_PS_WAIT_BCN,
00710     #endif //(MESH_PS_WAIT_BCN_DEF)
00711     #ifdef MESH_PS_LOCAL_MAW_DEF
00712     MESH_PS_LOCAL_MAW,
00713     #endif //(MESH_PS_LOCAL_MAW_DEF)
00714     #ifdef MESH_PS_PEER_MAW_DEF
00715     MESH_PS_PEER_MAW,
00716     #endif //(MESH_PS_PEER_MAW_DEF)
00717 
00718     #ifdef CPU_SLEEP_DEF
00719     CPU_SLEEP,
00720     #endif
00721     
00722     #ifdef DEEP_SLEEP_DEF
00723     DEEP_SLEEP,
00724     #endif
00725 
00726     #ifdef TDLS_CHSW_REQ_RX_DEF
00727     TDLS_RX_CHSW_REQ,
00728     #endif
00729     #ifdef TDLS_CHSW_RESP_RX_DEF
00730     TDLS_RX_CHSW_RESP,
00731     #endif
00732     #ifdef TDLS_CHSW_REQ_TX_DEF
00733     TDLS_TX_CHSW_REQ,
00734     #endif
00735     #ifdef TDLS_CHSW_RESP_TX_DEF
00736     TDLS_TX_CHSW_RESP,
00737     #endif
00738     #ifdef TDLS_SWITCH_TO_OFFCH_DEF
00739     TDLS_SWITCH_TO_OFFCH,
00740     #endif
00741     #ifdef TDLS_SWITCH_TO_BASECH_DEF
00742     TDLS_SWITCH_TO_BASECH,
00743     #endif
00744     #ifdef TDLS_CHSW_TIME_TIMER_DEF
00745     TDLS_CHSW_TIME_TIMER,
00746     #endif
00747     #ifdef TDLS_CHSW_TIMEOUT_TIMER_DEF
00748     TDLS_CHSW_TIMEOUT_TIMER,
00749     #endif
00750     #ifdef TDLS_CHSW_END_TIMER_DEF
00751     TDLS_CHSW_END_TIMER,
00752     #endif
00753     #ifdef TDLS_CHSW_REQ_TX_TIMER_DEF
00754     TDLS_CHSW_REQ_TX_TIMER,
00755     #endif
00756     #ifdef TDLS_DELAY_CHSW_DEF
00757     TDLS_DELAY_CHSW,
00758     #endif
00759     #ifdef TDLS_CHSW_NULL_FRAME_TX_DEF
00760     TDLS_TX_CHSW_NULL_FRAME,
00761     #endif
00762     #ifdef RTOS_TASK_DEF
00763     RTOS_TASK,
00764     RTOS_TASK_LAST = RTOS_TASK + 3,
00765     #endif
00766     #ifdef ANT_DIV_SWITCH_DEF
00767     ANT_DIV_SWITCH,
00768     #endif
00769     
00770     DBG_PROF_MAX
00771 };
00773 
00774 
00775 #if NX_PROFILING_ON
00777 extern const char * const dbg_prof_conf[DBG_PROF_MAX];
00778 #endif
00779 
00780 
00782 
00783 #endif // _DBG_PROFILING_H_
/space/home/slher/rel/Beken/v6_4_5/macsw/modules/dbg/src/dbg_profiling.h
