IPC
[PLATFORM]

Inter Processor Communication module. More...

Collaboration diagram for IPC:

Data Structures
struct	ipc_emb_env_tag
	Structure describing the IPC environment. More...
struct	ipc_header
	IPC header structure. More...
struct	ipc_msg_elt
	Structure of a IPC message. More...
struct	ipc_e2a_msg
	Message structure for MSGs from Emb to App. More...
struct	ipc_dbg_msg
	Message structure for Debug messages from Emb to App. More...
struct	ipc_a2e_msg
	Message structure for MSGs from App to Emb. More...
struct	ipc_shared_rx_buf
	Information provided by host to indentify RX buffer. More...
struct	ipc_shared_rx_desc
	Information provided by host to indentify RX desc. More...
struct	compatibility_tag
	Structure containing FW characteristics for compatibility checking. More...
struct	ipc_shared_env_tag
	Structure describing the IPC data shared with the host CPU. More...
Defines
#define	MSG_LLICTRL(irqenable) ( (irqenable)?(IPC_DMA_LLI_IRQ_EN\|(IPC_DMA_LLI_MSG << IPC_DMA_LLI_IRQ_POS)) : 0)
	Configure the DMA control field for a kernel message upload.
#define	DBG_LLICTRL(irqenable) ( (irqenable)?(IPC_DMA_LLI_IRQ_EN\|(IPC_DMA_LLI_DBG << IPC_DMA_LLI_IRQ_POS)) : 0)
	Configure the DMA control field for a debug message upload.
#define	ALL_EVENTS_TX
	Bit field containing all IPC TX event bits.
#define	HIGH_PRIO_EVT (KE_EVT_RXREADY_BIT \| KE_EVT_PRIMARY_TBTT_BIT \| KE_EVT_MACIF_TXDESC_BCN_BIT)
	High priority kernel that should interrupt the IPC TX event.
#define	IPC_TXQUEUE_CNT NX_TXQ_CNT
	Number of IPC TX queues.
#define	IPC_RXBUF_CNT 128
	Number of Host buffers available for Data Rx handling (through DMA).
#define	IPC_RXDESC_CNT 128
	Number of shared descriptors available for Data RX handling.
#define	IPC_RADARBUF_CNT 16
	Number of Host buffers available for Radar events handling (through DMA).
#define	IPC_UNSUPRXVECBUF_CNT 8
	Number of Host buffers available for unsupported rx vector handling (through DMA).
#define	IPC_RXBUF_SIZE 4096
	RX Data buffers size (in bytes).
#define	IPC_MSGE2A_BUF_CNT 64
	Number of Host buffers available for Emb->App MSGs sending (through DMA).
#define	IPC_DBGBUF_CNT 32
	Number of Host buffers available for Debug Messages sending (through DMA).
#define	IPC_A2E_MSG_BUF_SIZE 127
	Length used in APP2EMB MSGs structures.
#define	IPC_E2A_MSG_SIZE_BASE 256
	Length required in EMB2APP MSGs structures, for non-TL4 case.
#define	IPC_E2A_MSG_PARAM_SIZE IPC_E2A_MSG_SIZE_BASE
	Length used in EMB2APP MSGs structures, including the potential overhead for TL4.
#define	IPC_DBG_PARAM_SIZE 256
	Debug messages buffers size (in bytes).
#define	RX_DMA_OVER_PATTERN 0xAAAAAA00
	Define used for Rx hostbuf validity.
#define	IPC_MSGE2A_VALID_PATTERN 0xADDEDE2A
	Define used for MSG buffers validity.
#define	IPC_DBG_VALID_PATTERN 0x000CACA0
	Define used for Debug messages buffers validity.
#define	DMA_HDR_PHYVECT_LEN 36
	Length of the receive vectors, in bytes.
#define	MSG_API_VER 17
	Message struct/ID API version.
Functions
__INLINE void	ipc_emb_txdesc_copy (struct txdesc dst_local, volatile struct txdesc_host src_shared)
	Copy a TX descriptor from its shared RAM location to the CPU data memory.
uint8_t	ipc_emb_tx_q_len (int queue_idx, int vif_idx)
	Check how many tx descriptors are available on the requested queue for a VIF.
void	ipc_emb_init (void)
	Initialize the IPC on the embedded side.
void	ipc_emb_tx_flow_off (void)
	Stop the TX flow between the upper layers and the LMAC software.
void	ipc_emb_tx_flow_on (void)
	Restart the TX flow between the upper layers and the LMAC software.
void	ipc_emb_tx_irq (void)
	Handle Tx packet interrupt on the emb side.
void	ipc_emb_tx_evt (int queue_idx)
	Kernel event handler for the handling of the TX descriptor pushed by the host.
void	ipc_emb_cfmback_irq (void)
	IRQ handler.
static uint32_t	ipc_emb_hostmsgbuf_get (void)
	Retrieve a hostbuf address for future DMA transfer of a MSG.
static uint32_t	ipc_emb_hostdbgbuf_get (void)
	Retrieve a hostbuf address for future DMA transfer of a debug buffer.
uint32_t	ipc_emb_hostdbgdumpbuf_get (void)
	Retrieve a hostbuf address for debug dump transfer.
bool	ipc_emb_hostrxbuf_check (void)
	Checks if a host buffer is currently available.
uint32_t	ipc_emb_hostrxbuf_get (uint32_t *host_id)
	Retrieve a hostbuf address for future DMA transfer.
bool	ipc_emb_hostrxdesc_check (void)
	Check if a RX descriptor is available.
uint32_t	ipc_emb_hostrxdesc_get (void)
	Retrieve a host RX descriptor address for future DMA transfer.
uint32_t	ipc_emb_hostradarbuf_get (void)
	Retrieve a hostbuf address for future radar event DMA transfer.
void	ipc_emb_rxdata_ind (void)
	Sends an Data Reception Indication to the upper layer.
void	ipc_emb_radar_event_ind (void)
	Indicate to the upper side that at least one radar event is pending.
void	ipc_emb_txcfm_ind (uint32_t queue_bits)
	Indicate to the upper side that at least on confirmation is pending.
void	ipc_emb_prim_tbtt_ind (void)
	Indicate to the upper side that the primary TBTT is pending.
void	ipc_emb_sec_tbtt_ind (void)
	Indicate to the upper side that the secondary TBTT is pending.
static void	ipc_emb_kmsg_hdlr (struct ke_msg *kmsg_ipc)
	Copy and forward kernel messages received from the IPC to the destination task.
void	ipc_emb_msg_irq (void)
	IRQ handler.
void	ipc_emb_msg_evt (int dummy)
	EVT handler.
void	ipc_emb_kmsg_fwd (const struct ke_msg *ke_msg)
	Forward a kernel message to the host side (emb side).
void	ipc_emb_msg_dma_int_handler (void)
	Handles the DMA interrupt generated when the MSG from Embedded side to Application has been transferred.
void	ipc_emb_print_fwd (bool poll, const uint32_t len, char *string)
	Send an EMB string to the APP - IPC API function.
void	ipc_emb_dbg_dma_int_handler (void)
	Handles the DMA interrupt generated when the Debug message from Embedded side to Application has been transferred.
__INLINE uint32_t	ipc_emb_tx_pattern_addr_get (void)
	Get the host address of the TX payload descriptor pattern.
__INLINE uint32_t	ipc_emb_buffered_get (uint8_t sta, uint8_t tid)
	Get the buffered data from the IPC shared memory for a given sta/tid.
__INLINE bool	ipc_emb_tx_q_has_data (int queue_idx)
	Check if some TX descriptors are available on the requested queue.
__INLINE uint32_t	ipc_emb_tx_evt_field (uint32_t stat)
	Convert a TX descriptor interrupt status in to the corresponding kernel event bit field.
__INLINE void	ipc_emb_enable_users (int queue_idx, uint8_t active_users)
	Re-enable the user queues that were disabled.
Variables
const uint32_t	ipc_emb_evt_bit [NX_TXQ_CNT]
	Array of bits event to be triggered per TX queue index.
struct ipc_emb_env_tag	ipc_emb_env
	Global variable containing the IPC_EMB environment.
const int	nx_txdesc_cnt_msk []
	Mask for the indexes of the different queues.
struct ipc_emb_env_tag	ipc_emb_env
	Embedded IPC environment variable.
const int	nx_txdesc_cnt_msk []
	Mask of the TX descriptor length per queue.
struct ipc_shared_env_tag	ipc_shared_env
	IPC Shared environment.
APP2EMB IPC interrupt definitions

#define	IPC_IRQ_A2E_USER_MSK 0x3
	Interrupts bits used for the TX descriptors of the AC queues.
#define	IPC_IRQ_A2E_AC0_OFT 8
	Offset of the interrupts for AC0.
#define	IPC_IRQ_A2E_AC0_MSK (IPC_IRQ_A2E_USER_MSK << IPC_IRQ_A2E_AC0_OFT)
	Mask of the interrupts for AC0.
#define	IPC_IRQ_A2E_AC1_OFT (IPC_IRQ_A2E_AC0_OFT + RW_USER_MAX)
	Offset of the interrupts for AC1.
#define	IPC_IRQ_A2E_AC1_MSK (IPC_IRQ_A2E_USER_MSK << IPC_IRQ_A2E_AC1_OFT)
	Mask of the interrupts for AC1.
#define	IPC_IRQ_A2E_AC2_OFT (IPC_IRQ_A2E_AC1_OFT + RW_USER_MAX)
	Offset of the interrupts for AC2.
#define	IPC_IRQ_A2E_AC2_MSK (IPC_IRQ_A2E_USER_MSK << IPC_IRQ_A2E_AC2_OFT)
	Mask of the interrupts for AC2.
#define	IPC_IRQ_A2E_AC3_OFT (IPC_IRQ_A2E_AC2_OFT + RW_USER_MAX)
	Offset of the interrupts for AC3.
#define	IPC_IRQ_A2E_AC3_MSK (IPC_IRQ_A2E_USER_MSK << IPC_IRQ_A2E_AC3_OFT)
	Mask of the interrupts for AC3.
#define	IPC_IRQ_A2E_BCN_OFT (IPC_IRQ_A2E_AC3_OFT + RW_USER_MAX)
	Offset of the interrupts for BCN.
#define	IPC_IRQ_A2E_BCN_MSK CO_BIT(IPC_IRQ_A2E_BCN_OFT)
	Mask of the interrupts for BCN.
#define	IPC_IRQ_A2E_AC_TXDESC
	Interrupts bits used for the TX descriptors of the AC queues.
#define	IPC_IRQ_A2E_BCN_TXDESC (0x01 << IPC_IRQ_A2E_BCN_OFT)
	Interrupts bits used for the TX descriptors of the BCN queue.
#define	IPC_IRQ_A2E_TXDESC (IPC_IRQ_A2E_AC_TXDESC \| IPC_IRQ_A2E_BCN_TXDESC)
	IPC TX descriptor interrupt mask.
#define	IPC_IRQ_A2E_TXDESC_FIRSTBIT (8)
	First of the IPC TX descriptor interrupts.
#define	IPC_IRQ_A2E_RXBUF_BACK CO_BIT(5)
	IPC RX buffer allocation interrupt bit.
#define	IPC_IRQ_A2E_RXDESC_BACK CO_BIT(4)
	IPC RX buffer allocation interrupt bit.
#define	IPC_IRQ_A2E_MSG CO_BIT(1)
	IPC APP2EMB message interrupt bit.
#define	IPC_IRQ_A2E_DBG CO_BIT(0)
	IPC APP2EMB debug interrupt bit.
#define	IPC_IRQ_A2E_ALL (IPC_IRQ_A2E_TXDESC\|IPC_IRQ_A2E_MSG\|IPC_IRQ_A2E_DBG)
	IPC global interrupt mask.
EMB2APP IPC interrupt definitions

#define	IPC_IRQ_E2A_TXCFM_POS 7
	IPC TX confirmation interrupt bit position.
#define	IPC_IRQ_E2A_USER_MSK 0x3
	Interrupts bits used.
#define	IPC_IRQ_E2A_AC0_OFT 7
	Offset of the interrupts for AC0.
#define	IPC_IRQ_E2A_AC0_MSK (IPC_IRQ_E2A_USER_MSK << IPC_IRQ_E2A_AC0_OFT)
	Mask of the interrupts for AC0.
#define	IPC_IRQ_E2A_AC1_OFT (IPC_IRQ_E2A_AC0_OFT + RW_USER_MAX)
	Offset of the interrupts for AC1.
#define	IPC_IRQ_E2A_AC1_MSK (IPC_IRQ_E2A_USER_MSK << IPC_IRQ_E2A_AC1_OFT)
	Mask of the interrupts for AC1.
#define	IPC_IRQ_E2A_AC2_OFT (IPC_IRQ_E2A_AC1_OFT + RW_USER_MAX)
	Offset of the interrupts for AC2.
#define	IPC_IRQ_E2A_AC2_MSK (IPC_IRQ_E2A_USER_MSK << IPC_IRQ_E2A_AC2_OFT)
	Mask of the interrupts for AC2.
#define	IPC_IRQ_E2A_AC3_OFT (IPC_IRQ_E2A_AC2_OFT + RW_USER_MAX)
	Offset of the interrupts for AC3.
#define	IPC_IRQ_E2A_AC3_MSK (IPC_IRQ_E2A_USER_MSK << IPC_IRQ_E2A_AC3_OFT)
	Mask of the interrupts for AC3.
#define	IPC_IRQ_E2A_BCN_OFT (IPC_IRQ_E2A_AC3_OFT + RW_USER_MAX)
	Offset of the interrupts for BCN.
#define	IPC_IRQ_E2A_BCN_MSK CO_BIT(IPC_IRQ_E2A_BCN_OFT)
	Mask of the interrupts for BCN.
#define	IPC_IRQ_E2A_AC_TXCFM
	IPC TX confirmation interrupt bit position.
#define	IPC_IRQ_E2A_BCN_TXCFM (0x01 << IPC_IRQ_E2A_BCN_OFT)
	Interrupts bits used for the TX descriptors of the BCN queue.
#define	IPC_IRQ_E2A_TXCFM (IPC_IRQ_E2A_AC_TXCFM \| IPC_IRQ_E2A_BCN_TXCFM)
	IPC TX descriptor interrupt mask.
#define	IPC_IRQ_E2A_UNSUP_RX_VEC CO_BIT(7)
	IPC unsupported rx vector interrupt.
#define	IPC_IRQ_E2A_RADAR CO_BIT(6)
	IPC radar interrupt.
#define	IPC_IRQ_E2A_TBTT_SEC CO_BIT(5)
	IPC secondary TBTT interrupt.
#define	IPC_IRQ_E2A_TBTT_PRIM CO_BIT(4)
	IPC primary TBTT interrupt.
#define	IPC_IRQ_E2A_RXDESC CO_BIT(3)
	IPC RX descriptor interrupt.
#define	IPC_IRQ_E2A_MSG_ACK CO_BIT(2)
	IPC APP2EMB message acknowledgment interrupt.
#define	IPC_IRQ_E2A_MSG CO_BIT(1)
	IPC EMB2APP message interrupt.
#define	IPC_IRQ_E2A_DBG CO_BIT(0)
	IPC EMB2APP debug interrupt.
#define	IPC_IRQ_E2A_ALL
	IPC EMB2APP global interrupt mask.

Detailed Description

Inter Processor Communication module.

The IPC module implements the protocol to communicate between the Host CPU and the Embedded CPU.

A typical use case of the IPC Tx path API:

A typical use case of the IPC Rx path API:

Define Documentation

#define ALL_EVENTS_TX

Value:

(KE_EVT_MACIF_TXDESC_AC0_BIT | KE_EVT_MACIF_TXDESC_AC1_BIT |  \
                        KE_EVT_MACIF_TXDESC_AC2_BIT | KE_EVT_MACIF_TXDESC_AC3_BIT |  \
                        KE_EVT_MACIF_TXDESC_BCN_BIT)

Bit field containing all IPC TX event bits.

Definition at line 69 of file ipc_emb.c.

#define IPC_DBG_VALID_PATTERN 0x000CACA0

Define used for Debug messages buffers validity.

This value will be written only when a DBG buffer is used for sending from Emb to App.

Definition at line 178 of file ipc_shared.h.

#define IPC_IRQ_A2E_AC_TXDESC

Value:

(IPC_IRQ_A2E_AC0_MSK | IPC_IRQ_A2E_AC1_MSK | \
                                   IPC_IRQ_A2E_AC2_MSK | IPC_IRQ_A2E_AC3_MSK)

Interrupts bits used for the TX descriptors of the AC queues.

Interrupts bits used

Definition at line 408 of file ipc_shared.h.

#define IPC_IRQ_A2E_USER_MSK 0x3

Interrupts bits used for the TX descriptors of the AC queues.

Interrupts bits used

Definition at line 384 of file ipc_shared.h.

#define IPC_IRQ_E2A_AC_TXCFM

Value:

(IPC_IRQ_E2A_AC0_MSK | IPC_IRQ_E2A_AC1_MSK | \
                                   IPC_IRQ_E2A_AC2_MSK | IPC_IRQ_E2A_AC3_MSK)

IPC TX confirmation interrupt bit position.

Definition at line 487 of file ipc_shared.h.

#define IPC_IRQ_E2A_ALL

Value:

( IPC_IRQ_E2A_TXCFM         \
                                | IPC_IRQ_E2A_RXDESC        \
                                | IPC_IRQ_E2A_MSG_ACK       \
                                | IPC_IRQ_E2A_MSG           \
                                | IPC_IRQ_E2A_DBG           \
                                | IPC_IRQ_E2A_TBTT_PRIM     \
                                | IPC_IRQ_E2A_TBTT_SEC      \
                                | IPC_IRQ_E2A_RADAR         \
                                | IPC_IRQ_E2A_UNSUP_RX_VEC)

IPC EMB2APP global interrupt mask.

Definition at line 528 of file ipc_shared.h.

#define IPC_MSGE2A_VALID_PATTERN 0xADDEDE2A

Define used for MSG buffers validity.

This value will be written only when a MSG buffer is used for sending from Emb to App.

Definition at line 172 of file ipc_shared.h.

#define RX_DMA_OVER_PATTERN 0xAAAAAA00

Define used for Rx hostbuf validity.

This value should appear only when hostbuf was used for a Reception.

Definition at line 166 of file ipc_shared.h.

Function Documentation

__INLINE uint32_t ipc_emb_buffered_get	(	uint8_t	sta,
		uint8_t	tid
	)

Get the buffered data from the IPC shared memory for a given sta/tid.

Parameters:

`[in]`	sta	STA index
`[in]`	tid	TID

Returns:: number of bytes buffered

Definition at line 107 of file ipc_emb.h.

References ipc_shared_env_tag::buffered, and ipc_shared_env.

Referenced by macif_buffered_get().

void ipc_emb_cfmback_irq ( void )

IRQ handler.

Handle confirmation events interrupt on the emb side.

__INLINE void ipc_emb_enable_users	(	int	queue_idx,
		uint8_t	active_users
	)

Re-enable the user queues that were disabled.

Parameters:

`[in]`	queue_idx	Index of the TX queue
`[in]`	active_users	Bit field showing the users to re-enable

Definition at line 196 of file ipc_emb.h.

References ipc_emb_env, ipc_emb_tx_evt_field(), IPC_IRQ_A2E_TXDESC, IPC_IRQ_A2E_TXDESC_FIRSTBIT, ke_evt_set(), RW_USER_MAX, and ipc_emb_env_tag::user_active.

Referenced by macif_tx_enable_users().

static uint32_t ipc_emb_hostdbgbuf_get ( void ) [static]

Retrieve a hostbuf address for future DMA transfer of a debug buffer.

This function gives back the hostbuf address according to the current value of the msg buffer index. It just returns the pointer values set by the upper layer at init time and after each reception.

Returns:: Hostmsgbuf address.

Definition at line 590 of file ipc_emb.c.

References ipc_shared_env_tag::dbg_hostbuf_addr, ipc_emb_env_tag::ipc_dbg_buf_idx, IPC_DBGBUF_CNT, ipc_emb_env, and ipc_shared_env.

uint32_t ipc_emb_hostdbgdumpbuf_get ( void )

Retrieve a hostbuf address for debug dump transfer.

Returns:: Hostbuf address.

static uint32_t ipc_emb_hostmsgbuf_get ( void ) [static]

Retrieve a hostbuf address for future DMA transfer of a MSG.

This function gives back the hostbuf address according to the current value of the msg buffer index. It just returns the pointer values set by the upper layer at init time and after each reception.

Returns:: Hostmsgbuf address.

Definition at line 555 of file ipc_emb.c.

References ipc_emb_env, IPC_MSGE2A_BUF_CNT, ipc_emb_env_tag::ipc_msge2a_buf_idx, ipc_shared_env, and ipc_shared_env_tag::msg_e2a_hostbuf_addr.

uint32_t ipc_emb_hostradarbuf_get ( void )

Retrieve a hostbuf address for future radar event DMA transfer.

Returns:: Hostbuf address.

bool ipc_emb_hostrxbuf_check ( void )

Checks if a host buffer is currently available.

If no buffer is available, then the RX buffer pushed interrupt is enabled in order to be warned about a new buffer push when RX flow control is enabled.

Returns:: true if a buffer is available, false otherwise.

Referenced by macif_rx_buf_check().

uint32_t ipc_emb_hostrxbuf_get ( uint32_t * host_id )

Retrieve a hostbuf address for future DMA transfer.

This function gives back the hostbuf address according to the current value of the rx buffer index. It just returns the pointer values set by the upper layer at init time and after each reception. The buffer address in memory is then cleared and the FIFO index is incremented. The buffer is therefore not available anymore after the call. Prior to the call to this function, a call to ipc_emb_hostrxbuf_check has to be performed to ensure that there is a buffer available.

Parameters:

[out] host_id HostId linked to the buffer

Returns:: Hostbuf address.

Referenced by macif_rx_buf_get().

bool ipc_emb_hostrxdesc_check ( void )

Check if a RX descriptor is available.

Returns:: true if a descriptor is available, false otherwise.

Referenced by macif_rx_desc_upload().

uint32_t ipc_emb_hostrxdesc_get ( void )

Retrieve a host RX descriptor address for future DMA transfer.

Returns:: RX descriptor address.

Referenced by macif_rx_desc_upload().

void ipc_emb_init ( void )

Initialize the IPC on the embedded side.

Warning:: Since this function sets some Init values in IPC Shared memory it must not be called before ipc_host_init() which resets all IPC Shared memory at boot.

Set unchanged fields of the Debug DMA descriptor (to send strings to App)

void ipc_emb_kmsg_fwd ( const struct ke_msg * ke_msg )

Forward a kernel message to the host side (emb side).

Implementation of macif_kmsg_fwd when control layer is running on a remote host

Parameters:

[in] ke_msg Pointer on the message

Referenced by macif_kmsg_fwd().

static void ipc_emb_kmsg_hdlr ( struct ke_msg * kmsg_ipc ) [static]

Copy and forward kernel messages received from the IPC to the destination task.

Parameters:

[in] kmsg_ipc Address of the message in the shared memory

Definition at line 852 of file ipc_emb.c.

References ASSERT_ERR, ke_msg::dest_id, ke_msg::hdr, ke_msg::id, ipc_emb_env, IPC_IRQ_E2A_MSG_ACK, ipc_emb_env_tag::ipc_msgacke2a_cnt, ke_malloc(), ke_msg2param(), ke_msg_send(), ke_task_local(), co_list_hdr::next, ke_msg::param, ke_msg::param_len, and ke_msg::src_id.

void ipc_emb_msg_evt ( int dummy )

EVT handler.

Kernel event handler for the handling of messages pushed by the host.

Implementation of macif_msg_evt when control layer is running on a remote host

Parameters:

[in] dummy Parameter not used but required to follow the kernel event callback format

Referenced by macif_msg_evt().

void ipc_emb_msg_irq ( void )

IRQ handler.

Handle kernel message interrupt on the emb side.

void ipc_emb_prim_tbtt_ind ( void )

Indicate to the upper side that the primary TBTT is pending.

Implementation of macif_prim_tbtt_ind when control layer is running on a remote host

Referenced by macif_prim_tbtt_ind().

void ipc_emb_print_fwd	(	bool	poll,
		const uint32_t	len,
		char *	string
	)

Send an EMB string to the APP - IPC API function.

Parameters:

`[in]`	poll	Poll to ensure that print has gone when we exit the function
`[in]`	len	Length of the message
`[in]`	string	Pointer to the message Start must be word aligned (assumed to be the sprintf buffer) The string may be truncated if it is too long.

void ipc_emb_rxdata_ind ( void )

Sends an Data Reception Indication to the upper layer.

This function warns the upper layer about Data Reception through the setting of IPC_IRQ_E2A_RXDESC trigger.

Referenced by macif_rx_data_ind().

void ipc_emb_sec_tbtt_ind ( void )

Indicate to the upper side that the secondary TBTT is pending.

Implementation of macif_sec_tbtt_ind when control layer is running on a remote host

Referenced by macif_sec_tbtt_ind().

void ipc_emb_tx_evt ( int queue_idx )

Kernel event handler for the handling of the TX descriptor pushed by the host.

Parameters:

[in] queue_idx Index of the TX queues for which the event is called

Referenced by macif_tx_evt().

__INLINE uint32_t ipc_emb_tx_evt_field ( uint32_t stat )

Convert a TX descriptor interrupt status in to the corresponding kernel event bit field.

Parameters:

[in] stat TX descriptor interrupt status

Returns:: The bit field of kernel events

Definition at line 170 of file ipc_emb.h.

References IPC_IRQ_A2E_AC0_MSK, IPC_IRQ_A2E_AC1_MSK, IPC_IRQ_A2E_AC2_MSK, IPC_IRQ_A2E_AC3_MSK, IPC_IRQ_A2E_BCN_MSK, IPC_IRQ_A2E_TXDESC_FIRSTBIT, and NX_BEACONING.

Referenced by ipc_emb_enable_users().

void ipc_emb_tx_flow_off ( void )

Stop the TX flow between the upper layers and the LMAC software.

void ipc_emb_tx_flow_on ( void )

Restart the TX flow between the upper layers and the LMAC software.

void ipc_emb_tx_irq ( void )

Handle Tx packet interrupt on the emb side.

__INLINE uint32_t ipc_emb_tx_pattern_addr_get ( void )

Get the host address of the TX payload descriptor pattern.

Returns:: The address of the TX descriptor pattern

Definition at line 91 of file ipc_emb.h.

References ipc_shared_env, and ipc_shared_env_tag::pattern_addr.

Referenced by macif_tx_pattern_addr_get().

__INLINE bool ipc_emb_tx_q_has_data ( int queue_idx )

Check if some TX descriptors are available on the requested queue.

Parameters:

[in] queue_idx Index of the TX queue

Returns:: true if some descriptors are available, false otherwise

Definition at line 122 of file ipc_emb.h.

References ipc_emb_env, nx_txdesc_cnt_msk, nx_txuser_cnt, txdesc_host::ready, ipc_emb_env_tag::txdesc, and ipc_emb_env_tag::txdesc_idx.

Referenced by macif_tx_q_has_data().

uint8_t ipc_emb_tx_q_len	(	int	queue_idx,
		int	vif_idx
	)

Check how many tx descriptors are available on the requested queue for a VIF.

Parameters:

`[in]`	queue_idx	Index of the TX queue
`[in]`	vif_idx	Index of the Vif

Returns:: Number of txdesc ready on the TX queue for the specified vif

Referenced by macif_tx_q_len().

void ipc_emb_txcfm_ind ( uint32_t queue_bits )

Indicate to the upper side that at least on confirmation is pending.

Parameters:

[in] queue_bits Bitfields indicating for which queues confirmations are pending

Referenced by macif_tx_cfm_dma_int_handler().

__INLINE void ipc_emb_txdesc_copy	(	struct txdesc *	dst_local,
		volatile struct txdesc_host *	src_shared
	)

Copy a TX descriptor from its shared RAM location to the CPU data memory.

Parameters:

`[in]`	dst_local	Pointer to the destination in data memory
`[in]`	src_shared	Pointer to the source in shared RAM

Definition at line 128 of file ipc_emb.c.

References txdesc_host::api, txdesc::host, and sizeof_b.

Variable Documentation

struct ipc_emb_env_tag ipc_emb_env

Global variable containing the IPC_EMB environment.

Embedded IPC environment variable.

Definition at line 101 of file ipc_emb.c.

Referenced by ipc_emb_enable_users(), ipc_emb_hostdbgbuf_get(), ipc_emb_hostmsgbuf_get(), ipc_emb_kmsg_hdlr(), and ipc_emb_tx_q_has_data().

const uint32_t ipc_emb_evt_bit[NX_TXQ_CNT]

Initial value:

{

    [AC_BCN] = KE_EVT_MACIF_TXDESC_BCN_BIT,

    [AC_VO] = KE_EVT_MACIF_TXDESC_AC3_BIT,
    [AC_VI] = KE_EVT_MACIF_TXDESC_AC2_BIT,
    [AC_BE] = KE_EVT_MACIF_TXDESC_AC1_BIT,
    [AC_BK] = KE_EVT_MACIF_TXDESC_AC0_BIT,
}

Array of bits event to be triggered per TX queue index.

Definition at line 89 of file ipc_emb.c.

const int nx_txdesc_cnt_msk[]

Mask of the TX descriptor length per queue.

These values allow wrapping the TX descriptor indexes used to address the TX descriptor arrays in shared RAM.

Definition at line 104 of file ipc_emb.c.

Referenced by ipc_emb_tx_q_has_data().

const int nx_txdesc_cnt_msk[]

Initial value:

{
    NX_TXDESC_CNT0 - 1,
    NX_TXDESC_CNT1 - 1,
    NX_TXDESC_CNT2 - 1,
    NX_TXDESC_CNT3 - 1,

    NX_TXDESC_CNT4 - 1,

}

Mask for the indexes of the different queues.

Mask of the TX descriptor length per queue.

Definition at line 104 of file ipc_emb.c.

Referenced by ipc_emb_tx_q_has_data().

IPC [PLATFORM]

Data Structures

Defines

Functions

Variables

APP2EMB IPC interrupt definitions

EMB2APP IPC interrupt definitions

Detailed Description

Define Documentation

Function Documentation

Variable Documentation

IPC
[PLATFORM]