/space/home/slher/rel/Beken/v6_4_5/macsw/ip/lmac/src/hal/hal_desc.h

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#ifndef _HAL_DESC_H_
#define _HAL_DESC_H_

/*
 * INCLUDE FILES
 ****************************************************************************************
 */
#include "co_int.h"
// for mac_addr
#include "mac.h"
// for mac frame definitions
#include "mac_frame.h"
// for dma_desc
#include "dma.h"
// for CO_BIT
#include "co_math.h"
// for co_list_hdr
#include "co_list.h"
// for phy_channel_info
#include "phy.h"
// for DBG info format
#include "dbg.h"
#if (NX_RADAR_DETECT || NX_UF_EN)
// for hal_dma_desc
#include "hal_dma.h"
#endif //(NX_RADAR_DETECT)

/*
 * DEFINES
 ****************************************************************************************
 */
#define RADAR_PULSE_MAX   4
#define RADAR_EVENT_MAX   10
#define UNSUP_RX_VECT_MAX   8

#define TX_HEADER_DESC_PATTERN 0xCAFEBABE
#define TX_PAYLOAD_DESC_PATTERN 0xCAFEFADE
#define RX_HEADER_DESC_PATTERN 0xBAADF00D
#define RX_PAYLOAD_DESC_PATTERN 0xC0DEDBAD

#if NX_MON_DATA
#define RX_MACHDR_BACKUP_LEN    64
#endif

//----------------------------------------------------------------------------------------
// TBD: BUF CONTROL INFO definitions
//----------------------------------------------------------------------------------------
#define TBD_DONE_HW             CO_BIT(31)
#define TBD_INTERRUPT_EN        CO_BIT(0)

//----------------------------------------------------------------------------------------
// THD: PHY CONTROL INFO definitions
//----------------------------------------------------------------------------------------
#if !NX_MAC_HE
#define SOUNDING_TX_BIT         CO_BIT(0)
#define SMOOTHING_TX_BIT        CO_BIT(1)
#define SMOOTHING_PROT_TX_BIT   CO_BIT(2)
#endif
#define USE_BW_SIG_TX_BIT       CO_BIT(3)
#define DYN_BW_TX_BIT           CO_BIT(4)
#define DOZE_ALLOWED_TX_BIT     CO_BIT(5)
#define CONT_TX_BIT             CO_BIT(6)
#define USER_POS_OFT            12
#define USER_POS_MASK           (0x3 << USER_POS_OFT)
#define USE_RIFS_TX_BIT         CO_BIT(14)
#define USE_MUMIMO_TX_BIT       CO_BIT(15)
#define GID_TX_OFT              16
#define GID_TX_MASK             (0x3F << GID_TX_OFT)
#define PAID_TX_OFT             22
#define PAID_TX_MASK            (0x1FF << PAID_TX_OFT)

//----------------------------------------------------------------------------------------
// THD: MAC CONTROL INFO 1 definitions
//----------------------------------------------------------------------------------------
#define PROT_FRM_DURATION_OFT             16
#define PROT_FRM_DURATION_MSK             (0xFFFF << PROT_FRM_DURATION_OFT)

#define WRITE_ACK                         CO_BIT(14)
#define LOW_RATE_RETRY                    CO_BIT(13)
#define LSTP_PROT                         CO_BIT(12)
#define LSTP                              CO_BIT(11)

// Expected Acknowledgment
#define EXPECTED_ACK_OFT                  9
#define EXPECTED_ACK_MSK                  (0x3 << EXPECTED_ACK_OFT)
#define EXPECTED_ACK_NO_ACK               (0x0 << EXPECTED_ACK_OFT)
#define EXPECTED_ACK_NORMAL_ACK           (0x1 << EXPECTED_ACK_OFT)
#define EXPECTED_ACK_BLOCK_ACK            (0x2 << EXPECTED_ACK_OFT)
#define EXPECTED_ACK_COMPRESSED_BLOCK_ACK (0x3 << EXPECTED_ACK_OFT)

//----------------------------------------------------------------------------------------
// THD MACCTRLINFO2 fields
//----------------------------------------------------------------------------------------
#define TS_VALID_BIT                      CO_BIT(0)

#define FRM_TYPE_OFT                      1
#define FRM_TYPE_MSK                      (0x3<<FRM_TYPE_OFT)

#define FRM_TYPE_MNG                      (0<<FRM_TYPE_OFT)
#define FRM_TYPE_CNTL                     (1<<FRM_TYPE_OFT)
#define FRM_TYPE_DATA                     (2<<FRM_TYPE_OFT)

#define FRM_SUBTYPE_OFT                   3
#define FRM_SUBTYPE_MSK                   (0xF<<FRM_SUBTYPE_OFT)

#define FRM_CNTL_SUBTYPE_BAR              (8<<FRM_SUBTYPE_OFT)
#define FRM_CNTL_SUBTYPE_BA               (9<<FRM_SUBTYPE_OFT)

#define INTERRUPT_EN_TX                   CO_BIT(8)

#define NB_BLANK_DELIM_OFT                9
#define NB_BLANK_DELIM_MSK                (0x3FF << NB_BLANK_DELIM_OFT)

#define WHICHDESC_OFT                     19
#define WHICHDESC_MSK                     (0x07 << WHICHDESC_OFT)
#define WHICHDESC_UNFRAGMENTED_MSDU       (0x00 << WHICHDESC_OFT)
#define WHICHDESC_FRAGMENTED_MSDU_FIRST   (0x01 << WHICHDESC_OFT)
#define WHICHDESC_FRAGMENTED_MSDU_INT     (0x02 << WHICHDESC_OFT)
#define WHICHDESC_FRAGMENTED_MSDU_LAST    (0x03 << WHICHDESC_OFT)
#define WHICHDESC_AMPDU_EXTRA             (0x04 << WHICHDESC_OFT)
#define WHICHDESC_AMPDU_FIRST             (0x05 << WHICHDESC_OFT)
#define WHICHDESC_AMPDU_INT               (0x06 << WHICHDESC_OFT)
#define WHICHDESC_AMPDU_LAST              (0x07 << WHICHDESC_OFT)

#define AMPDU_OFT                         21
#define AMPDU_BIT                         CO_BIT(AMPDU_OFT)

#define UNDER_BA_SETUP_BIT                CO_BIT(22)

#define DONT_TOUCH_DUR                    CO_BIT(28)


//----------------------------------------------------------------------------------------
//THD STATINFO fields
//----------------------------------------------------------------------------------------
#define NUM_RTS_RETRIES_OFT                0
#define NUM_RTS_RETRIES_MSK               (0xFF << NUM_RTS_RETRIES_OFT)
#define NUM_MPDU_RETRIES_OFT               8
#define NUM_MPDU_RETRIES_MSK              (0xFF << NUM_MPDU_RETRIES_OFT)
#define RETRY_LIMIT_REACHED_BIT            CO_BIT(16)
#define LIFETIME_EXPIRED_BIT               CO_BIT(17)
#define BA_FRAME_RECEIVED_BIT              CO_BIT(18)
#define HE_TB_TX_BIT                       CO_BIT(22)
#define FRAME_SUCCESSFUL_TX_BIT            CO_BIT(23)
#define A_MPDU_LAST                        (0x0F << 26)
#define BW_TX_OFT                          24
#define BW_TX_MSK                          (0x3 << BW_TX_OFT)
#define BW_20MHZ_TX                        (0x0 << BW_TX_OFT)
#define BW_40MHZ_TX                        (0x1 << BW_TX_OFT)
#define BW_80MHZ_TX                        (0x2 << BW_TX_OFT)
#define BW_160MHZ_TX                       (0x3 << BW_TX_OFT)
#define DESC_DONE_TX_BIT                   CO_BIT(31)
#define DESC_DONE_SW_TX_BIT                CO_BIT(30)


#define RATE_CONTROL_STEPS      4

#define POLICY_TABLE_PATTERN    0xBADCAB1E

// Policy Table: PHY Control 1 Information field
#if NX_MAC_HE
#define SOUNDING_TX_OFT         0
#define SOUNDING_TX_BIT         CO_BIT(SOUNDING_TX_OFT)
#define SMOOTHING_TX_OFT        1
#define SMOOTHING_TX_BIT        CO_BIT(SMOOTHING_TX_OFT)
#define SMOOTHING_PROT_TX_OFT   2
#define SMOOTHING_PROT_TX_BIT   CO_BIT(SMOOTHING_PROT_TX_OFT)
#endif
#define BF_FORM_EXT_PT_OFT      3
#define BF_FORM_EXT_PT_MASK     (0x1 << BF_FORM_EXT_PT_OFT)
#define NO_EXTN_SS_PT_OFT       4
#define NO_EXTN_SS_PT_MASK      (0x3 << NO_EXTN_SS_PT_OFT)
#define FEC_CODING_PT_OFT       6
#define FEC_CODING_PT_BIT       CO_BIT(FEC_CODING_PT_OFT)
#define STBC_PT_OFT             7
#define STBC_PT_MASK            (0x3 << STBC_PT_OFT)
#define NX_TX_PT_OFT            14
#define NX_TX_PT_MASK           (0x7 << NX_TX_PT_OFT)
#define NX_TX_PROT_PT_OFT       17
#define NX_TX_PROT_PT_MASK      (0x7 << NX_TX_PROT_PT_OFT)
#define DOPPLER_OFT             20
#define DOPPLER_BIT             CO_BIT(DOPPLER_OFT)
#define SPATIAL_REUSE_OFT       24
#define SPATIAL_REUSE_MASK      (0xF << SPATIAL_REUSE_OFT)

// Policy Table: PHY Control 2 Information field
#define ANTENNA_SET_PT_OFT      0
#define ANTENNA_SET_PT_MASK     0XFF
#define SMM_INDEX_PT_OFT        8
#define SMM_INDEX_PT_MASK       (0XFF << SMM_INDEX_PT_OFT)
#define BMFED_OFT               16
#define BMFED_BIT               CO_BIT(BMFED_OFT)
#define BMCHANGE_OFT            17
#define BMCHANGE_BIT            CO_BIT(BMCHANGE_OFT)
#define UPLINK_FLAG_OFT         18
#define UPLINK_FLAG_BIT         CO_BIT(UPLINK_FLAG_OFT)
#define BSS_COLOR_OFT           20
#define BSS_COLOR_MASK         (0X3F << BSS_COLOR_OFT)
#define PKT_EXTENSION_OFT       26
#define PKT_EXTENSION_MASK     (0X07 << PKT_EXTENSION_OFT)

// Policy Table: MAC Control 1 Information field
#define KEYSRAM_INDEX_OFT       0
#define KEYSRAM_INDEX_MASK      (0X3FF << KEYSRAM_INDEX_OFT)
#define KEYSRAM_INDEX_RA_OFT    10
#define KEYSRAM_INDEX_RA_MASK   (0X3FF << KEYSRAM_INDEX_RA_OFT)

// Policy Table: MAC Control 2 Information field.
#define LONG_RETRY_LIMIT_OFT    0
#define LONG_RETRY_LIMIT_MASK   (0XFF << LONG_RETRY_LIMIT_OFT)
#define SHORT_RETRY_LIMIT_OFT   8
#define SHORT_RETRY_LIMIT_MASK  (0XFF << SHORT_RETRY_LIMIT_OFT)
#define RTS_THRSHOLD_OFT        16 // Bits 16-23
#define RTS_THRSHOLD_MASK       (0XFF << RTS_THRSHOLD_OFT)

// Policy Table: Rate Control Information field
#define MCS_INDEX_TX_RCX_OFT    0
#define MCS_INDEX_TX_RCX_MASK   (0X7F << MCS_INDEX_TX_RCX_OFT)
#define BW_TX_RCX_OFT           7
#define BW_TX_RCX_MASK          (0X3 << BW_TX_RCX_OFT)
#define SHORT_GI_TX_RCX_OFT     9
#define SHORT_GI_TX_RCX_MASK    (0x1 << SHORT_GI_TX_RCX_OFT)
#define PRE_TYPE_TX_RCX_OFT     10
#define PRE_TYPE_TX_RCX_MASK    (0x1 << PRE_TYPE_TX_RCX_OFT)
#define HE_GI_TYPE_TX_RCX_OFT   9
#define HE_GI_TYPE_TX_RCX_MASK  (0x3 << HE_GI_TYPE_TX_RCX_OFT)
#define GI_TYPE_0_8             (0x0 << HE_GI_TYPE_TX_RCX_OFT)
#define GI_TYPE_1_6             (0x1 << HE_GI_TYPE_TX_RCX_OFT)
#define GI_TYPE_3_2             (0x2 << HE_GI_TYPE_TX_RCX_OFT)
#define FORMAT_MOD_TX_RCX_OFT   11
#define FORMAT_MOD_TX_RCX_MASK  (0X7 << FORMAT_MOD_TX_RCX_OFT)
#define PROT_FRM_EX_RCX_OFT     14
#define PROT_FRM_EX_RCX_MASK    (0X7 << PROT_FRM_EX_RCX_OFT)
#define PROT_NO_PROT            (0x0 << PROT_FRM_EX_RCX_OFT)
#define PROT_SELF_CTS           (0x1 << PROT_FRM_EX_RCX_OFT)
#define PROT_RTS_CTS            (0x2 << PROT_FRM_EX_RCX_OFT)
#define PROT_RTS_CTS_WITH_QAP   (0x3 << PROT_FRM_EX_RCX_OFT)
#define PROT_STBC               (0x4 << PROT_FRM_EX_RCX_OFT)

#define MCS_INDEX_PROT_TX_RCX_OFT  17
#define MCS_INDEX_PROT_TX_RCX_MASK (0x7F << MCS_INDEX_PROT_TX_RCX_OFT)
#define BW_PROT_TX_RCX_OFT      24
#define BW_PROT_TX_RCX_MASK     (0x3 << BW_PROT_TX_RCX_OFT)
#define FORMAT_MOD_PROT_TX_RCX_OFT  26
#define FORMAT_MOD_PROT_TX_RCX_MASK (0x7 << FORMAT_MOD_PROT_TX_RCX_OFT)
#define N_RETRY_RCX_OFT         29
#define N_RETRY_RCX_MASK        (0x7 << N_RETRY_RCX_OFT)

// Values of the FORMAT_MOD fields
#define FORMATMOD_NON_HT          0
#define FORMATMOD_NON_HT_DUP_OFDM 1
#define FORMATMOD_HT_MF           2
#define FORMATMOD_HT_GF           3
#define FORMATMOD_VHT             4
#define FORMATMOD_HE_SU           5
#define FORMATMOD_HE_MU           6
#define FORMATMOD_HE_ER           7

#define BW_20MHZ                  0
#define BW_40MHZ                  1
#define BW_80MHZ                  2
#define BW_160MHZ                 3

// VHT specific NSS and MCS values
#define VHT_NSS_OFT               4
#define VHT_NSS_MASK              (0x7 << VHT_NSS_OFT)
#define VHT_MCS_OFT               0
#define VHT_MCS_MASK              (0xF << VHT_MCS_OFT)

// HT specific NSS and MCS values (valid only for MCS <= 31)
#define HT_NSS_OFT               3
#define HT_NSS_MASK              (0x3 << HT_NSS_OFT)
#define HT_MCS_OFT               0
#define HT_MCS_MASK              (0x7 << HT_MCS_OFT)

// Policy Table: Power Control Information field
#define TX_PWR_LEVEL_PT_RCX_OFT         0
#define TX_PWR_LEVEL_PT_RCX_MASK        (0xff << TX_PWR_LEVEL_PT_RCX_OFT)
#define TX_PWR_LEVEL_PROT_PT_RCX_OFT    8
#define TX_PWR_LEVEL_PROT_PT_RCX_MASK   (0xff << TX_PWR_LEVEL_PROT_PT_RCX_OFT)
#define TX_PWR_LEVEL_MASK               (TX_PWR_LEVEL_PT_RCX_MASK | TX_PWR_LEVEL_PROT_PT_RCX_MASK)
#define TX_PWR_LEVEL_SET(pwr)           (((pwr) << TX_PWR_LEVEL_PROT_PT_RCX_OFT) |       \
                                         ((pwr) << TX_PWR_LEVEL_PT_RCX_OFT))
#define TX_HE_LTF_TYPE_PT_RCX_OFT       16
#define TX_HE_LTF_TYPE_PT_RCX_MASK      (0x03 << TX_HE_LTF_TYPE_PT_RCX_OFT)
#define TX_1x_HE_LTF_FOR_3_2_US         (0x00 << TX_HE_LTF_TYPE_PT_RCX_OFT)
#define TX_2x_HE_LTF_FOR_6_4_US         (0x01 << TX_HE_LTF_TYPE_PT_RCX_OFT)
#define TX_4x_HE_LTF_FOR_12_8_US        (0x02 << TX_HE_LTF_TYPE_PT_RCX_OFT)
#define TX_HE_DCM_OFT                   18
#define TX_HE_DCM_BIT                   CO_BIT(TX_HE_DCM_OFT)


// Compressed Policy Table: Secondary User Information field
#define MCS_IDX_TX_CPT_OFT      0
#define MCS_IDX_TX_CPT_MASK     (0x7F << MCS_IDX_TX_CPT_OFT)
#define FEC_CODING_CPT_OFT      7
#define FEC_CODING_CPT_BIT      CO_BIT(FEC_CODING_CPT_OFT)
#define SMM_INDEX_CPT_OFT       8
#define SMM_INDEX_CPT_MASK      (0XFF << SMM_INDEX_CPT_OFT)
#define KEYSRAM_INDEX_CPT_OFT   16
#define KEYSRAM_INDEX_CPT_MASK  (0X3FF << KEYSRAM_INDEX_OFT)



#define KEY_IDX_OFT                       15
#define KEY_IDX_MSK                       (0x3FF << KEY_IDX_OFT)
#define KEY_IDX_VALID_BIT                 CO_BIT(25)
#define IMM_RSP_AC_OFT                    11
#define IMM_RSP_AC_MSK                    (0x03 << IMM_RSP_AC_OFT)

#define RX_PD_LASTBUF 0x0001
#define RX_PD_DONE 0x0002

#define RX_HD_KEYIDV 0x02000000
#define RX_HD_KEYID 0x01FF8000
#define RX_HD_KEYID_LSB 15
#define RX_HD_DONE 0x00004000
#define RX_HD_SUCCESS 0x00002000
#define RX_HD_GA_FRAME 0x00000400
#define RX_HD_ADDRMIS 0x00000200
#define RX_HD_FCSERR 0x0100
#if NX_RX_RING
#define RX_HD_UNDEF_ERR 0x00000080
#define RX_HD_DECR_ERR 0x00000040
#define RX_HD_DECRTYPE_MSK 0x0000003C
#define RX_HD_DECRTYPE_OFT 2
#define RX_HD_DECR_UNENC (0x00 << RX_HD_DECRTYPE_OFT)
#define RX_HD_DECR_WEP (0x01 << RX_HD_DECRTYPE_OFT)
#define RX_HD_DECR_TKIP (0x02 << RX_HD_DECRTYPE_OFT)
#define RX_HD_DECR_CCMP128 (0x03 << RX_HD_DECRTYPE_OFT)
#define RX_HD_DECR_CCMP256 (0x04 << RX_HD_DECRTYPE_OFT)
#define RX_HD_DECR_GCMP128 (0x05 << RX_HD_DECRTYPE_OFT)
#define RX_HD_DECR_GCMP256 (0x06 << RX_HD_DECRTYPE_OFT)
#define RX_HD_DECR_WAPI (0x07 << RX_HD_DECRTYPE_OFT)
#define RX_HD_DECR_UNK (0x0F << RX_HD_DECRTYPE_OFT)
#define RX_HD_DECRSTATUS (RX_HD_DECR_ERR | RX_HD_DECRTYPE_MSK)
#define RX_HD_DECR_WEP_SUCCESS (RX_HD_DECR_WEP)
#define RX_HD_DECR_TKIP_SUCCESS (RX_HD_DECR_TKIP)
#define RX_HD_DECR_CCMP128_SUCCESS (RX_HD_DECR_CCMP128)
#define RX_HD_DECR_CCMP256_SUCCESS (RX_HD_DECR_CCMP256)
#define RX_HD_DECR_GCMP128_SUCCESS (RX_HD_DECR_GCMP128)
#define RX_HD_DECR_GCMP256_SUCCESS (RX_HD_DECR_GCMP256)
#define RX_HD_DECR_WAPI_SUCCESS (RX_HD_DECR_WAPI)
#else
#define RX_HD_PHY_ERR 0x00000080
#define RX_HD_UNDEF_ERR 0x00000040
#define RX_HD_DECRSTATUS 0x0000001C
#define RX_HD_DECR_UNENC 0x0000
#define RX_HD_DECR_WEP_SUCCESS 0x0014
#define RX_HD_DECR_TKIP_SUCCESS 0x0018
#define RX_HD_DECR_CCMP128_SUCCESS 0x001C
#endif
#define RX_HD_RSP_FRM 0x00000002
#define RX_HD_RXVEC2V 0x00000001
#define RX_HD_KEYID_GET(__s) (((__s) & RX_HD_KEYID) >> RX_HD_KEYID_LSB)
#define RX_HD_DONE_GET(__s) ((__s) & RX_HD_DONE)
#define RX_HD_SUCCESS_GET(__s) ((__s) & (RX_HD_SUCCESS | RX_HD_FCSERR))


#define RXL_HWDESC_RXV_LEN    40




#define RXVEC1_NUM_REG      4

#if (NX_MAC_VER >= 20)
#define RXVEC_FORMATMOD(__x)   (((__x) & 0x0000000F))
#define RXVEC_PRETYPE(__x)     (((__x) & 0x00000080) >> 7)
#define RXVEC_LEGRATE(__x)     (((__x) & 0x000000F0) >> 4)
#ifdef CFG_RWTL
#define RXVEC_RSSI1(__x)       ((int32_t)((__x) & 0x0000FF00) >> 8)
#else
#define RXVEC_RSSI1(__x)       (((__x) & 0x0000FF00) >> 8)
#endif
#define RXVEC_HTLENGTH_0(__x)    (((__x) & 0x0000FFFF))
#else
#define RXVEC_LEGRATE(__x)     (((__x) & 0x0000F000) >> 12)
#define RXVEC_HTLENGTH_0(__x)    (((__x) & 0xFFFF0000) >> 16)
#define RXVEC_HTLENGTH_1(__x)    (((__x) & 0x0000000F))
#define RXVEC_PRETYPE(__x)     (((__x) & 0x00008000) >> 15)
#define RXVEC_FORMATMOD(__x)   (((__x) & 0x00070000) >> 16)
#ifdef CFG_RWTL
#define RXVEC_RSSI1(__x)       ((int32_t)((__x) & 0xFF000000) >> 24)
#else
#define RXVEC_RSSI1(__x)       (((__x) & 0xFF000000) >> 24)
#endif
#ifdef CFG_RWTL
#define RXVEC_RSSI2(__x)       ((int32_t)(((__x) & 0x000000FF) << 24) >> 24)
#else
#define RXVEC_RSSI2(__x)       (((__x) & 0x000000FF))
#endif
#endif // (NX_MAC_VER >= 20)


#define RX_AMPDU_AMPDUCNT(__x)   (((__x) & 0xC000) >> 14)
#define RX_AMPDU_MPDUCNT(__x)    ((__x) & 0x3F00)


enum
{
    HW_RATE_1MBPS = 0,
    HW_RATE_2MBPS,
    HW_RATE_5_5MBPS,
    HW_RATE_11MBPS,
    HW_RATE_6MBPS,
    HW_RATE_9MBPS,
    HW_RATE_12MBPS,
    HW_RATE_18MBPS,
    HW_RATE_24MBPS,
    HW_RATE_36MBPS,
    HW_RATE_48MBPS,
    HW_RATE_54MBPS
};

struct machdr
{
    uint16_t reserved;
    uint16_t framectrl;
    uint16_t duration;
    struct mac_addr macaddr1;
    struct mac_addr macaddr2;
    struct mac_addr macaddr3;
    uint16_t seq_ctrl;
    struct mac_addr macaddr4;
    uint16_t qos_ctrl;
    uint16_t carriedfr_ctrl;
    uint32_t ht_ctrl;
    uint32_t iv;
    uint32_t ext_iv;
};

struct tx_policy_tbl
{
    uint32_t upatterntx;
    uint32_t phycntrlinfo1;
    uint32_t phycntrlinfo2;
    uint32_t maccntrlinfo1;
    uint32_t maccntrlinfo2;
    uint32_t ratecntrlinfo[RATE_CONTROL_STEPS];
    uint32_t powercntrlinfo[RATE_CONTROL_STEPS];
};

struct tx_compressed_policy_tbl
{
    uint32_t upatterntx;
    uint32_t sec_user_control;
};

struct tx_hd
{
    uint32_t             upatterntx;
    uint32_t             nextfrmexseq_ptr;
    uint32_t             nextmpdudesc_ptr;
    union {
        uint32_t             first_pbd_ptr;
        uint32_t             sec_user1_ptr;
    };
    union {
        uint32_t             datastartptr;
        uint32_t             sec_user2_ptr;
    };
    union {
        uint32_t             dataendptr;
        uint32_t             sec_user3_ptr;
    };
    uint32_t             frmlen;
    uint32_t             frmlifetime;
    uint32_t             phyctrlinfo;
    uint32_t             policyentryaddr;
    uint32_t             optlen[3];
    uint32_t             macctrlinfo1;
    uint32_t             macctrlinfo2;
    uint32_t             statinfo;
    uint32_t             mediumtimeused;
};

struct tx_pbd
{
    uint32_t             upatterntx;
    uint32_t             next;
    uint32_t             datastartptr;
    uint32_t             dataendptr;
    uint32_t             bufctrlinfo;
};

struct tx_dmadesc
{
    struct tx_hd header;
    struct tx_pbd buffer;
    struct machdr macheader;
};

struct rx_vector_1
{
    uint32_t            recvec1a;
    uint32_t            recvec1b;
    uint32_t            recvec1c;
    uint32_t            recvec1d;
};

struct rx_vector_2
{
    uint32_t            recvec2a;
    uint32_t            recvec2b;
};

struct rx_hd
{
    uint32_t            upatternrx;
    uint32_t            next;
    uint32_t            first_pbd_ptr;
    struct rxdesc      *rxdesc;
    uint32_t            datastartptr;
    uint32_t            dataendptr;
    uint32_t            headerctrlinfo;
    uint16_t            frmlen;
    uint16_t            ampdu_stat_info;
    uint32_t            tsflo;
    uint32_t            tsfhi;
    struct rx_vector_1  rx_vec_1;
    struct rx_vector_2  rx_vec_2;
    uint32_t            statinfo;
};

struct rx_pbd
{
    uint32_t            upattern;
    uint32_t            next;
    uint32_t            datastartptr;
    uint32_t            dataendptr;
    uint16_t            bufstatinfo;
    uint16_t            reserved;
};

#if NX_MON_DATA
struct rxu_machdrdesc
{
    uint32_t buf_len;
    uint32_t buffer[RX_MACHDR_BACKUP_LEN / 4];
};
#endif

struct rx_dmadesc
{
    struct rx_hd hd;
    struct phy_channel_info phy_info;
    #if NX_UMAC_PRESENT
    uint32_t flags;
    #if NX_AMSDU_DEAGG
    uint32_t amsdu_hostids[NX_MAX_MSDU_PER_RX_AMSDU - 1];
    #endif
    #if NX_MON_DATA
    struct rxu_machdrdesc mac_hdr_backup;
    #endif
    #endif
    uint32_t pattern;
    struct dma_desc dma_desc;
};

struct rx_payloaddesc
{
    struct rx_pbd pbd;
    struct dma_desc dma_desc[NX_DMADESC_PER_RX_PDB_CNT];
    #if !NX_RX_RING
    uint32_t buffer[NX_RX_PAYLOAD_LEN/4];
    #endif
};

struct tx_cfm_tag
{
    #if NX_UMAC_PRESENT
    #if !NX_FULLY_HOSTED
    uint16_t pn[4];
    uint16_t sn;
    uint16_t timestamp;
    #endif
    int8_t credits;
    uint8_t ampdu_size;
    #if NX_AMSDU_TX
    uint16_t amsdu_size;
    #endif
    #endif

    uint32_t status;
};

struct tx_hw_desc
{
    #if !NX_FULLY_HOSTED
    struct tx_cfm_tag cfm;
    struct dma_desc dma_desc;
    #endif
    struct tx_hd    thd;
};

#if NX_RADAR_DETECT
struct radar_pulse_array_desc
{
    struct phy_radar_pulse pulse[RADAR_PULSE_MAX];
    uint32_t idx;
    uint32_t cnt;
};

struct radar_event_desc
{
    struct co_list_hdr list_hdr;
    struct dma_desc dma_desc;
    struct hal_dma_desc_tag gp_dma_desc;
    struct radar_pulse_array_desc pulse_array;
};
#endif

#if NX_UF_EN
struct rx_vector_desc
{
    struct phy_channel_info phy_info;

    struct rx_vector_1 rx_vec_1;
    #if !NX_FULLY_HOSTED
    uint32_t pattern;
    #endif // !NX_FULLY_HOSTED
};

struct unsup_rx_vector_desc
{
    struct co_list_hdr list_hdr;
    #if !NX_FULLY_HOSTED
    struct dma_desc dma_desc;
    struct hal_dma_desc_tag gp_dma_desc;
    #endif // !NX_FULLY_HOSTED
    struct rx_vector_desc rx_vector;
};
#endif

struct debug_info_tag
{
    volatile struct dma_desc dma_desc;
    struct dbg_debug_info_tag dbg_info;
};

/*
 * GLOBAL VARIABLES
 ****************************************************************************************
 */
#if NX_RADAR_DETECT
extern struct radar_event_desc radar_event_desc_array[RADAR_EVENT_MAX];
#endif

#if NX_UF_EN
extern struct unsup_rx_vector_desc rx_vector_desc_array[UNSUP_RX_VECT_MAX];
#endif

#if NX_BCN_AUTONOMOUS_TX
extern struct dma_desc bcn_dwnld_desc;
#endif

extern struct tx_hw_desc       tx_hw_desc0[RW_USER_MAX * NX_TXDESC_CNT0];
extern struct tx_hw_desc       tx_hw_desc1[RW_USER_MAX * NX_TXDESC_CNT1];
extern struct tx_hw_desc       tx_hw_desc2[RW_USER_MAX * NX_TXDESC_CNT2];
extern struct tx_hw_desc       tx_hw_desc3[RW_USER_MAX * NX_TXDESC_CNT3];
#if (NX_BEACONING)
extern struct tx_hw_desc       tx_hw_desc4[NX_TXDESC_CNT4];
#endif

#if NX_DEBUG_DUMP
extern struct debug_info_tag   debug_info;
#endif

__INLINE int8_t hal_desc_get_rssi(struct rx_vector_1 *rx_vec_1, int8_t *rx_rssi)
{
        int8_t rssi;

        #if (NX_MAC_VER >= 20)
        rx_rssi[0] = RXVEC_RSSI1(rx_vec_1->recvec1b);
        rx_rssi[1] = RXVEC_RSSI1(rx_vec_1->recvec1b);
        #else
        rx_rssi[0] = RXVEC_RSSI1(rx_vec_1->recvec1c);
        rx_rssi[1] = RXVEC_RSSI2(rx_vec_1->recvec1d);
        #endif // (NX_MAC_VER >= 20)

        // Set the RSSI value
        if (phy_get_nrx() == 1)
        {
           rssi = (rx_rssi[0] + rx_rssi[1])/2;
        }
        else
        {
           rssi = rx_rssi[0];
        }

        return rssi;
}

__INLINE uint16_t hal_desc_get_ht_length(struct rx_vector_1 *rx_vec_1)
{
    uint16_t length;

    #if (NX_MAC_VER >= 20)
    length = RXVEC_HTLENGTH_0(rx_vec_1->recvec1c);
    #else
    length = RXVEC_HTLENGTH_0(rx_vec_1->recvec1a);
    #endif // (NX_MAC_VER >= 20)

    return length;
}

__INLINE uint8_t hal_desc_get_rx_format(struct rx_vector_1 *rx_vec_1)
{
    uint8_t format;

    #if (NX_MAC_VER >= 20)
    format = RXVEC_FORMATMOD(rx_vec_1->recvec1a);
    #else
    format = RXVEC_FORMATMOD(rx_vec_1->recvec1b);
    #endif // (NX_MAC_VER >= 20)

    return format;
}

__INLINE uint8_t hal_desc_get_preamble_type(struct rx_vector_1 *rx_vec_1)
{
    uint8_t pretype;

    #if (NX_MAC_VER >= 20)
    pretype = RXVEC_PRETYPE(rx_vec_1->recvec1a);
    #else
    pretype = RXVEC_PRETYPE(rx_vec_1->recvec1b);
    #endif // (NX_MAC_VER >= 20)

    return pretype;
}

__INLINE uint8_t hal_desc_get_legacy_rate(struct rx_vector_1 *rx_vec_1)
{
    uint8_t rate;

    #if (NX_MAC_VER >= 20)
    rate = RXVEC_LEGRATE(rx_vec_1->recvec1b);
    #else
    rate = RXVEC_LEGRATE(rx_vec_1->recvec1a);
    #endif // (NX_MAC_VER >= 20)

    return rate;
}

#endif // _HWIF_DESC_H_

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