00001
00017 #ifndef _HAL_MACHW_H_
00018 #define _HAL_MACHW_H_
00019
00037 #include "hal_desc.h"
00038 #include "reg_mac_core.h"
00039
00040
00041
00042
00043
00044
00045
00047 #define HAL_MACHW_BCN_TX_DELAY_US (2048)
00048
00049 #if RW_MUMIMO_TX_EN
00051 #define MU_MIMO_MASTER_TX_IRQ NXMAC_SEC_USER_TX_TRIGGER_BIT
00053 #define TX_SEC_IRQ_BITS ( NXMAC_SEC_U_3AC_3_TX_BUF_TRIGGER_BIT | \
00054 NXMAC_SEC_U_3AC_2_TX_BUF_TRIGGER_BIT | \
00055 NXMAC_SEC_U_3AC_1_TX_BUF_TRIGGER_BIT | \
00056 NXMAC_SEC_U_3AC_0_TX_BUF_TRIGGER_BIT | \
00057 NXMAC_SEC_U_3AC_3_TX_TRIGGER_BIT | \
00058 NXMAC_SEC_U_3AC_2_TX_TRIGGER_BIT | \
00059 NXMAC_SEC_U_3AC_1_TX_TRIGGER_BIT | \
00060 NXMAC_SEC_U_3AC_0_TX_TRIGGER_BIT | \
00061 NXMAC_SEC_U_2AC_3_TX_BUF_TRIGGER_BIT | \
00062 NXMAC_SEC_U_2AC_2_TX_BUF_TRIGGER_BIT | \
00063 NXMAC_SEC_U_2AC_1_TX_BUF_TRIGGER_BIT | \
00064 NXMAC_SEC_U_2AC_0_TX_BUF_TRIGGER_BIT | \
00065 NXMAC_SEC_U_2AC_3_TX_TRIGGER_BIT | \
00066 NXMAC_SEC_U_2AC_2_TX_TRIGGER_BIT | \
00067 NXMAC_SEC_U_2AC_1_TX_TRIGGER_BIT | \
00068 NXMAC_SEC_U_2AC_0_TX_TRIGGER_BIT | \
00069 NXMAC_SEC_U_1AC_3_TX_BUF_TRIGGER_BIT | \
00070 NXMAC_SEC_U_1AC_2_TX_BUF_TRIGGER_BIT | \
00071 NXMAC_SEC_U_1AC_1_TX_BUF_TRIGGER_BIT | \
00072 NXMAC_SEC_U_1AC_0_TX_BUF_TRIGGER_BIT | \
00073 NXMAC_SEC_U_1AC_3_TX_TRIGGER_BIT | \
00074 NXMAC_SEC_U_1AC_2_TX_TRIGGER_BIT | \
00075 NXMAC_SEC_U_1AC_1_TX_TRIGGER_BIT | \
00076 NXMAC_SEC_U_1AC_0_TX_TRIGGER_BIT )
00077 #else
00078 #define MU_MIMO_MASTER_TX_IRQ 0
00079 #endif
00080
00081
00082
00083
00084
00085
00087 enum
00088 {
00090 HW_IDLE = 0,
00092 HW_RESERVED,
00094 HW_DOZE,
00096 HW_ACTIVE
00097 };
00098
00100 enum
00101 {
00103 MODE_802_11B = 0,
00105 MODE_802_11A,
00107 MODE_802_11G,
00109 MODE_802_11N_2_4,
00111 MODE_802_11N_5,
00113 MODE_RESERVED,
00115 MODE_802_11AC_5
00116 };
00117
00119 enum
00120 {
00122 HAL_AC0_TIMER = 0,
00124 HAL_AC1_TIMER,
00126 HAL_AC2_TIMER,
00128 HAL_AC3_TIMER,
00130 HAL_BCN_TIMER,
00131 #if NX_MAC_HE
00133 HAL_HE_TB_TIMER,
00134 #endif
00136 HAL_IDLE_TIMER,
00137 #if !NX_FULLY_HOSTED
00139 HAL_RX_TIMER,
00140 #endif
00141 #if NX_MM_TIMER
00143 HAL_MM_TIMER,
00144 #endif
00146 HAL_KE_TIMER,
00147
00149 HAL_TIMER_MAX,
00150 };
00151
00153 enum
00154 {
00156 HAL_AC0_TIMER_BIT = CO_BIT(HAL_AC0_TIMER),
00158 HAL_AC1_TIMER_BIT = CO_BIT(HAL_AC1_TIMER),
00160 HAL_AC2_TIMER_BIT = CO_BIT(HAL_AC2_TIMER),
00162 HAL_AC3_TIMER_BIT = CO_BIT(HAL_AC3_TIMER),
00164 HAL_BCN_TIMER_BIT = CO_BIT(HAL_BCN_TIMER),
00165 #if NX_MAC_HE
00167 HAL_HE_TB_TIMER_BIT = CO_BIT(HAL_HE_TB_TIMER),
00168 #endif
00170 HAL_IDLE_TIMER_BIT = CO_BIT(HAL_IDLE_TIMER),
00171 #if !NX_FULLY_HOSTED
00173 HAL_RX_TIMER_BIT = CO_BIT(HAL_RX_TIMER),
00174 #endif
00175 #if NX_MM_TIMER
00177 HAL_MM_TIMER_BIT = CO_BIT(HAL_MM_TIMER),
00178 #endif
00180 HAL_KE_TIMER_BIT = CO_BIT(HAL_KE_TIMER),
00181 };
00182
00183
00184
00185
00186
00187 #ifdef CFG_RWTL
00188 extern uint32_t tl_diff;
00189 #endif
00190
00198 __INLINE uint32_t hal_machw_time(void)
00199 {
00200 return nxmac_monotonic_counter_2_lo_get();
00201 }
00202
00213 __INLINE bool hal_machw_time_cmp(uint32_t time1, uint32_t time2)
00214 {
00215 uint32_t diff = time1 - time2;
00216
00217 #ifdef CFG_RWTL
00219 tl_diff = diff;
00220 #endif
00221
00222 return (((int32_t)diff) < 0);
00223 }
00224
00234 __INLINE bool hal_machw_time_past(uint32_t time)
00235 {
00236 return (hal_machw_time_cmp(time, hal_machw_time()));
00237 }
00238
00246 __INLINE void hal_machw_udelay(uint32_t us)
00247 {
00248 uint32_t e = hal_machw_time() + us;
00249 while (!hal_machw_time_past(e));
00250 }
00251
00252 #if NX_MULTI_ROLE
00253 extern const uint8_t rxv2macrate[];
00254
00265 __INLINE uint32_t hal_machw_rx_bcn_duration(struct rx_hd *rhd, uint16_t len)
00266 {
00267
00268 if (hal_desc_get_rx_format(&rhd->rx_vec_1) != 0)
00269 return 500;
00270
00271
00272 nxmac_ppdu_mcs_index_setf(rxv2macrate[hal_desc_get_legacy_rate(&rhd->rx_vec_1)]);
00273 #if (NX_MAC_VER >= 20)
00274 nxmac_time_on_air_param_1_pack(0, 0, 0, 0, hal_desc_get_preamble_type(&rhd->rx_vec_1), len);
00275 #else
00276 nxmac_time_on_air_param_1_pack(0, 0, 0, hal_desc_get_preamble_type(&rhd->rx_vec_1), 0, len);
00277 #endif // (NX_MAC_VER >= 20)
00278
00279
00280 nxmac_compute_duration_setf(1);
00281 #ifdef CFG_RWTL
00282
00283 hal_machw_time();
00284 #endif
00285 while(nxmac_time_on_air_valid_getf() == 0);
00286 ASSERT_REC_VAL(nxmac_time_on_air_valid_getf() != 0, 500);
00287
00288
00289 return ((uint32_t)nxmac_time_on_air_getf());
00290 }
00291 #endif
00292
00300 __INLINE bool hal_machw_bfmee_support(void)
00301 {
00302 return (nxmac_bfmee_getf() && phy_bfmee_supported()) != 0;
00303 }
00304
00312 __INLINE bool hal_machw_bfmer_support(void)
00313 {
00314 return (nxmac_bfmer_getf() && phy_bfmer_supported()) != 0;
00315 }
00316
00324 __INLINE bool hal_machw_mu_mimo_rx_support(void)
00325 {
00326 return (nxmac_bfmee_getf() && phy_mu_mimo_rx_supported()) != 0;
00327 }
00328
00336 __INLINE bool hal_machw_mu_mimo_tx_support(void)
00337 {
00338 return (nxmac_mu_mimo_tx_getf() && phy_mu_mimo_tx_supported()) != 0;
00339 }
00340
00348 __INLINE bool hal_machw_he_support(void)
00349 {
00350 #if !NX_MAC_HE
00351 return false;
00352 #else
00353 return (nxmac_he_getf() && phy_he_supported()) != 0;
00354 #endif
00355 }
00356
00363 void hal_machw_init(void);
00364
00365 #if NX_DEBUG_DUMP
00366
00371 void hal_machw_get_diag_state(void);
00372 #endif
00373
00381 void hal_machw_reset(void);
00382
00393 uint8_t hal_machw_search_addr(struct mac_addr *addr);
00394
00402 void hal_machw_disable_int(void);
00403
00404
00411 void hal_machw_stop(void);
00412
00419 void hal_machw_monitor_mode(void);
00420
00432 int hal_machw_tsf_move(int32_t offset);
00433
00441 bool hal_machw_sleep_check(void);
00442
00449 void hal_machw_gen_handler(void);
00450
00457 void hal_machw_idle_req(void);
00458
00461 #endif // _HAL_MACHW_H_