Shared data between both IPC modules. More...
#include "co_int.h"#include "tx_swdesc.h"Go to the source code of this file.
Data Structures | |
| struct | ipc_header |
| IPC header structure. More... | |
| struct | ipc_msg_elt |
| Structure of a IPC message. More... | |
| struct | ipc_e2a_msg |
| Message structure for MSGs from Emb to App. More... | |
| struct | ipc_dbg_msg |
| Message structure for Debug messages from Emb to App. More... | |
| struct | ipc_a2e_msg |
| Message structure for MSGs from App to Emb. More... | |
| struct | ipc_shared_rx_buf |
| Information provided by host to indentify RX buffer. More... | |
| struct | ipc_shared_rx_desc |
| Information provided by host to indentify RX desc. More... | |
| struct | compatibility_tag |
| Structure containing FW characteristics for compatibility checking. More... | |
| struct | ipc_shared_env_tag |
| Structure describing the IPC data shared with the host CPU. More... | |
Defines | |
| #define | IPC_TXQUEUE_CNT NX_TXQ_CNT |
| Number of IPC TX queues. | |
| #define | IPC_RXBUF_CNT 128 |
| Number of Host buffers available for Data Rx handling (through DMA). | |
| #define | IPC_RXDESC_CNT 128 |
| Number of shared descriptors available for Data RX handling. | |
| #define | IPC_RADARBUF_CNT 16 |
| Number of Host buffers available for Radar events handling (through DMA). | |
| #define | IPC_UNSUPRXVECBUF_CNT 8 |
| Number of Host buffers available for unsupported rx vector handling (through DMA). | |
| #define | IPC_RXBUF_SIZE 4096 |
| RX Data buffers size (in bytes). | |
| #define | IPC_MSGE2A_BUF_CNT 64 |
| Number of Host buffers available for Emb->App MSGs sending (through DMA). | |
| #define | IPC_DBGBUF_CNT 32 |
| Number of Host buffers available for Debug Messages sending (through DMA). | |
| #define | IPC_A2E_MSG_BUF_SIZE 127 |
| Length used in APP2EMB MSGs structures. | |
| #define | IPC_E2A_MSG_SIZE_BASE 256 |
| Length required in EMB2APP MSGs structures, for non-TL4 case. | |
| #define | IPC_E2A_MSG_PARAM_SIZE IPC_E2A_MSG_SIZE_BASE |
| Length used in EMB2APP MSGs structures, including the potential overhead for TL4. | |
| #define | IPC_DBG_PARAM_SIZE 256 |
| Debug messages buffers size (in bytes). | |
| #define | RX_DMA_OVER_PATTERN 0xAAAAAA00 |
| Define used for Rx hostbuf validity. | |
| #define | IPC_MSGE2A_VALID_PATTERN 0xADDEDE2A |
| Define used for MSG buffers validity. | |
| #define | IPC_DBG_VALID_PATTERN 0x000CACA0 |
| Define used for Debug messages buffers validity. | |
| #define | DMA_HDR_PHYVECT_LEN 36 |
| Length of the receive vectors, in bytes. | |
| #define | MSG_API_VER 17 |
| Message struct/ID API version. | |
APP2EMB IPC interrupt definitions | |
| #define | IPC_IRQ_A2E_USER_MSK 0x3 |
| Interrupts bits used for the TX descriptors of the AC queues. | |
| #define | IPC_IRQ_A2E_AC0_OFT 8 |
| Offset of the interrupts for AC0. | |
| #define | IPC_IRQ_A2E_AC0_MSK (IPC_IRQ_A2E_USER_MSK << IPC_IRQ_A2E_AC0_OFT) |
| Mask of the interrupts for AC0. | |
| #define | IPC_IRQ_A2E_AC1_OFT (IPC_IRQ_A2E_AC0_OFT + RW_USER_MAX) |
| Offset of the interrupts for AC1. | |
| #define | IPC_IRQ_A2E_AC1_MSK (IPC_IRQ_A2E_USER_MSK << IPC_IRQ_A2E_AC1_OFT) |
| Mask of the interrupts for AC1. | |
| #define | IPC_IRQ_A2E_AC2_OFT (IPC_IRQ_A2E_AC1_OFT + RW_USER_MAX) |
| Offset of the interrupts for AC2. | |
| #define | IPC_IRQ_A2E_AC2_MSK (IPC_IRQ_A2E_USER_MSK << IPC_IRQ_A2E_AC2_OFT) |
| Mask of the interrupts for AC2. | |
| #define | IPC_IRQ_A2E_AC3_OFT (IPC_IRQ_A2E_AC2_OFT + RW_USER_MAX) |
| Offset of the interrupts for AC3. | |
| #define | IPC_IRQ_A2E_AC3_MSK (IPC_IRQ_A2E_USER_MSK << IPC_IRQ_A2E_AC3_OFT) |
| Mask of the interrupts for AC3. | |
| #define | IPC_IRQ_A2E_BCN_OFT (IPC_IRQ_A2E_AC3_OFT + RW_USER_MAX) |
| Offset of the interrupts for BCN. | |
| #define | IPC_IRQ_A2E_BCN_MSK CO_BIT(IPC_IRQ_A2E_BCN_OFT) |
| Mask of the interrupts for BCN. | |
| #define | IPC_IRQ_A2E_AC_TXDESC |
| Interrupts bits used for the TX descriptors of the AC queues. | |
| #define | IPC_IRQ_A2E_BCN_TXDESC (0x01 << IPC_IRQ_A2E_BCN_OFT) |
| Interrupts bits used for the TX descriptors of the BCN queue. | |
| #define | IPC_IRQ_A2E_TXDESC (IPC_IRQ_A2E_AC_TXDESC | IPC_IRQ_A2E_BCN_TXDESC) |
| IPC TX descriptor interrupt mask. | |
| #define | IPC_IRQ_A2E_TXDESC_FIRSTBIT (8) |
| First of the IPC TX descriptor interrupts. | |
| #define | IPC_IRQ_A2E_RXBUF_BACK CO_BIT(5) |
| IPC RX buffer allocation interrupt bit. | |
| #define | IPC_IRQ_A2E_RXDESC_BACK CO_BIT(4) |
| IPC RX buffer allocation interrupt bit. | |
| #define | IPC_IRQ_A2E_MSG CO_BIT(1) |
| IPC APP2EMB message interrupt bit. | |
| #define | IPC_IRQ_A2E_DBG CO_BIT(0) |
| IPC APP2EMB debug interrupt bit. | |
| #define | IPC_IRQ_A2E_ALL (IPC_IRQ_A2E_TXDESC|IPC_IRQ_A2E_MSG|IPC_IRQ_A2E_DBG) |
| IPC global interrupt mask. | |
EMB2APP IPC interrupt definitions | |
| #define | IPC_IRQ_E2A_TXCFM_POS 7 |
| IPC TX confirmation interrupt bit position. | |
| #define | IPC_IRQ_E2A_USER_MSK 0x3 |
| Interrupts bits used. | |
| #define | IPC_IRQ_E2A_AC0_OFT 7 |
| Offset of the interrupts for AC0. | |
| #define | IPC_IRQ_E2A_AC0_MSK (IPC_IRQ_E2A_USER_MSK << IPC_IRQ_E2A_AC0_OFT) |
| Mask of the interrupts for AC0. | |
| #define | IPC_IRQ_E2A_AC1_OFT (IPC_IRQ_E2A_AC0_OFT + RW_USER_MAX) |
| Offset of the interrupts for AC1. | |
| #define | IPC_IRQ_E2A_AC1_MSK (IPC_IRQ_E2A_USER_MSK << IPC_IRQ_E2A_AC1_OFT) |
| Mask of the interrupts for AC1. | |
| #define | IPC_IRQ_E2A_AC2_OFT (IPC_IRQ_E2A_AC1_OFT + RW_USER_MAX) |
| Offset of the interrupts for AC2. | |
| #define | IPC_IRQ_E2A_AC2_MSK (IPC_IRQ_E2A_USER_MSK << IPC_IRQ_E2A_AC2_OFT) |
| Mask of the interrupts for AC2. | |
| #define | IPC_IRQ_E2A_AC3_OFT (IPC_IRQ_E2A_AC2_OFT + RW_USER_MAX) |
| Offset of the interrupts for AC3. | |
| #define | IPC_IRQ_E2A_AC3_MSK (IPC_IRQ_E2A_USER_MSK << IPC_IRQ_E2A_AC3_OFT) |
| Mask of the interrupts for AC3. | |
| #define | IPC_IRQ_E2A_BCN_OFT (IPC_IRQ_E2A_AC3_OFT + RW_USER_MAX) |
| Offset of the interrupts for BCN. | |
| #define | IPC_IRQ_E2A_BCN_MSK CO_BIT(IPC_IRQ_E2A_BCN_OFT) |
| Mask of the interrupts for BCN. | |
| #define | IPC_IRQ_E2A_AC_TXCFM |
| IPC TX confirmation interrupt bit position. | |
| #define | IPC_IRQ_E2A_BCN_TXCFM (0x01 << IPC_IRQ_E2A_BCN_OFT) |
| Interrupts bits used for the TX descriptors of the BCN queue. | |
| #define | IPC_IRQ_E2A_TXCFM (IPC_IRQ_E2A_AC_TXCFM | IPC_IRQ_E2A_BCN_TXCFM) |
| IPC TX descriptor interrupt mask. | |
| #define | IPC_IRQ_E2A_UNSUP_RX_VEC CO_BIT(7) |
| IPC unsupported rx vector interrupt. | |
| #define | IPC_IRQ_E2A_RADAR CO_BIT(6) |
| IPC radar interrupt. | |
| #define | IPC_IRQ_E2A_TBTT_SEC CO_BIT(5) |
| IPC secondary TBTT interrupt. | |
| #define | IPC_IRQ_E2A_TBTT_PRIM CO_BIT(4) |
| IPC primary TBTT interrupt. | |
| #define | IPC_IRQ_E2A_RXDESC CO_BIT(3) |
| IPC RX descriptor interrupt. | |
| #define | IPC_IRQ_E2A_MSG_ACK CO_BIT(2) |
| IPC APP2EMB message acknowledgment interrupt. | |
| #define | IPC_IRQ_E2A_MSG CO_BIT(1) |
| IPC EMB2APP message interrupt. | |
| #define | IPC_IRQ_E2A_DBG CO_BIT(0) |
| IPC EMB2APP debug interrupt. | |
| #define | IPC_IRQ_E2A_ALL |
| IPC EMB2APP global interrupt mask. | |
Variables | |
| struct ipc_shared_env_tag | ipc_shared_env |
| IPC Shared environment. | |
Shared data between both IPC modules.
Copyright (C) RivieraWaves 2011-2019
Definition in file ipc_shared.h.
1.6.1