/space/home/slher/rel/Beken/v6_4_5/macsw/plf/refip/src/driver/ipc/ipc_shared.h

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#ifndef _IPC_SHARED_H_
#define _IPC_SHARED_H_

/*
 * INCLUDE FILES
 ****************************************************************************************
 */
#ifndef __KERNEL__
#include "co_int.h"
#include "tx_swdesc.h"
#else
#include "dbg_assert.h"
#include "lmac_mac.h"
#endif

/*
 * DEFINES AND MACROS
 ****************************************************************************************
 */
#define IPC_TXQUEUE_CNT     NX_TXQ_CNT

#define IPC_RXBUF_CNT       128

#if (NX_UMAC_PRESENT)
#define IPC_RXDESC_CNT      128
#endif //(NX_UMAC_PRESENT)

#define IPC_RADARBUF_CNT       16

#define IPC_UNSUPRXVECBUF_CNT   8

#define IPC_RXBUF_SIZE 4096

#if NX_UMAC_PRESENT
#define IPC_MSGE2A_BUF_CNT       64
#else
#define IPC_MSGE2A_BUF_CNT       4
#endif

#define IPC_DBGBUF_CNT       32

#ifdef CFG_RWTL
#define IPC_A2E_MSG_BUF_SIZE    127 // size in 4-byte words
#else
#define IPC_A2E_MSG_BUF_SIZE    127 // size in 4-byte words
#endif

#if NX_UMAC_PRESENT
#define IPC_E2A_MSG_SIZE_BASE   256 // size in 4-byte words
#else
#define IPC_E2A_MSG_SIZE_BASE   15 // size in 4-byte words
#endif

#ifdef CFG_RWTL
#define IPC_E2A_MSG_PARAM_SIZE   (IPC_E2A_MSG_SIZE_BASE + (IPC_E2A_MSG_SIZE_BASE / 2))
#else
#define IPC_E2A_MSG_PARAM_SIZE   IPC_E2A_MSG_SIZE_BASE
#endif

#define IPC_DBG_PARAM_SIZE       256

#define RX_DMA_OVER_PATTERN 0xAAAAAA00

#define IPC_MSGE2A_VALID_PATTERN 0xADDEDE2A

#define IPC_DBG_VALID_PATTERN 0x000CACA0

#define DMA_HDR_PHYVECT_LEN    36

#define MSG_API_VER     17

struct ipc_header
{
    uint16_t type;
    uint16_t size;
};

struct ipc_msg_elt
{
    struct ipc_header header __ALIGN4;
};

struct ipc_e2a_msg
{
    uint16_t id;                
    uint16_t dummy_dest_id;     
    uint16_t dummy_src_id;      
    uint16_t param_len;         
    uint32_t param[IPC_E2A_MSG_PARAM_SIZE];  
    uint32_t pattern;           
};

struct ipc_dbg_msg
{
    uint32_t string[IPC_DBG_PARAM_SIZE/4]; 
    uint32_t pattern;                    
};

struct ipc_a2e_msg
{
    uint32_t dummy_word;                
    uint32_t msg[IPC_A2E_MSG_BUF_SIZE]; 
};

#if (NX_UMAC_PRESENT)
struct ipc_shared_rx_buf
{
    uint32_t hostid;
    uint32_t dma_addr;
};

struct ipc_shared_rx_desc
{
    uint32_t dma_addr;
};
#endif //(NX_UMAC_PRESENT)

/*
 * TYPE and STRUCT DEFINITIONS
 ****************************************************************************************
 */

struct compatibility_tag {
    uint16_t ipc_shared_size;
    uint16_t msg_api;
    uint8_t ipc_shared_version;
    uint8_t msge2a_buf_cnt;
    uint8_t dbgbuf_cnt;
    uint8_t radarbuf_cnt;
    uint8_t unsuprxvecbuf_cnt;
    uint8_t rxdesc_cnt;
    uint8_t rxbuf_cnt;
    uint8_t bk_txq;
    uint8_t be_txq;
    uint8_t vi_txq;
    uint8_t vo_txq;
    uint8_t bcn_txq;
};

// Indexes are defined in the MIB shared structure
struct ipc_shared_env_tag
{
    volatile struct compatibility_tag comp_info;

    volatile struct ipc_a2e_msg msg_a2e_buf;

    volatile struct    ipc_e2a_msg msg_e2a_buf;
    volatile struct    dma_desc msg_dma_desc;
    volatile uint32_t  msg_e2a_hostbuf_addr [IPC_MSGE2A_BUF_CNT];

    volatile struct    ipc_dbg_msg dbg_buf;
    volatile struct    dma_desc dbg_dma_desc;
    volatile uint32_t  dbg_hostbuf_addr [IPC_DBGBUF_CNT];

    volatile uint32_t  la_dbginfo_addr;

    volatile uint32_t  pattern_addr;

    volatile uint32_t  radarbuf_hostbuf [IPC_RADARBUF_CNT]; // buffers @ for Radar Events

    volatile uint32_t unsuprxvecbuf_hostbuf [IPC_UNSUPRXVECBUF_CNT];

    volatile struct txdesc_host txdesc0[RW_USER_MAX][NX_TXDESC_CNT0];
    volatile struct txdesc_host txdesc1[RW_USER_MAX][NX_TXDESC_CNT1];
    volatile struct txdesc_host txdesc2[RW_USER_MAX][NX_TXDESC_CNT2];
    volatile struct txdesc_host txdesc3[RW_USER_MAX][NX_TXDESC_CNT3];
    #if (NX_BEACONING)
    volatile struct txdesc_host txdesc4[1][NX_TXDESC_CNT4];
    #endif

    #if (NX_UMAC_PRESENT)
    volatile struct ipc_shared_rx_desc host_rxdesc[IPC_RXDESC_CNT];
    volatile struct ipc_shared_rx_buf  host_rxbuf[IPC_RXBUF_CNT];
    #else
    volatile uint32_t host_rxbuf[IPC_RXBUF_CNT];
    #endif //(NX_UMAC_PRESENT)

    volatile uint32_t buffered[NX_REMOTE_STA_MAX][TID_MAX];
    volatile uint16_t trace_pattern;
    volatile uint32_t trace_start;
    volatile uint32_t trace_end;
    volatile uint32_t trace_size;
    volatile uint32_t trace_offset;
    volatile uint32_t trace_nb_compo;
    volatile uint32_t trace_offset_compo;
};

extern struct ipc_shared_env_tag ipc_shared_env;

/*
 * TYPE and STRUCT DEFINITIONS
 ****************************************************************************************
 */


#if RW_MUMIMO_TX_EN
#ifdef CFG_IPC_VER_V10
#error "MU-MIMO cannot be compiled for old IPC"
#endif
#if RW_USER_MAX > 3
#define IPC_IRQ_A2E_USER_MSK       0xF
#elif RW_USER_MAX > 2
#define IPC_IRQ_A2E_USER_MSK       0x7
#else
#define IPC_IRQ_A2E_USER_MSK       0x3
#endif

#define IPC_IRQ_A2E_AC0_OFT        8
#define IPC_IRQ_A2E_AC0_MSK       (IPC_IRQ_A2E_USER_MSK << IPC_IRQ_A2E_AC0_OFT)
#define IPC_IRQ_A2E_AC1_OFT       (IPC_IRQ_A2E_AC0_OFT + RW_USER_MAX)
#define IPC_IRQ_A2E_AC1_MSK       (IPC_IRQ_A2E_USER_MSK << IPC_IRQ_A2E_AC1_OFT)
#define IPC_IRQ_A2E_AC2_OFT       (IPC_IRQ_A2E_AC1_OFT + RW_USER_MAX)
#define IPC_IRQ_A2E_AC2_MSK       (IPC_IRQ_A2E_USER_MSK << IPC_IRQ_A2E_AC2_OFT)
#define IPC_IRQ_A2E_AC3_OFT       (IPC_IRQ_A2E_AC2_OFT + RW_USER_MAX)
#define IPC_IRQ_A2E_AC3_MSK       (IPC_IRQ_A2E_USER_MSK << IPC_IRQ_A2E_AC3_OFT)
#define IPC_IRQ_A2E_BCN_OFT       (IPC_IRQ_A2E_AC3_OFT + RW_USER_MAX)
#define IPC_IRQ_A2E_BCN_MSK       CO_BIT(IPC_IRQ_A2E_BCN_OFT)

#define IPC_IRQ_A2E_AC_TXDESC     (IPC_IRQ_A2E_AC0_MSK | IPC_IRQ_A2E_AC1_MSK | \
                                   IPC_IRQ_A2E_AC2_MSK | IPC_IRQ_A2E_AC3_MSK)

#if !NX_BEACONING || (NX_BCN_AUTONOMOUS_TX && !NX_UMAC_PRESENT)
#define IPC_IRQ_A2E_BCN_TXDESC      0
#else
#define IPC_IRQ_A2E_BCN_TXDESC      (0x01 << IPC_IRQ_A2E_BCN_OFT)
#endif

#define IPC_IRQ_A2E_TXDESC          (IPC_IRQ_A2E_AC_TXDESC | IPC_IRQ_A2E_BCN_TXDESC)

#else /* !RW_MUMIMO_TX_EN */

#if !NX_BEACONING || (NX_BCN_AUTONOMOUS_TX && !NX_UMAC_PRESENT)
#define IPC_IRQ_A2E_TXDESC          0x0F00
#else
#define IPC_IRQ_A2E_TXDESC          0x1F00
#endif

#endif /* RW_MUMIMO_TX_EN */

#define IPC_IRQ_A2E_TXDESC_FIRSTBIT (8)
#define IPC_IRQ_A2E_RXBUF_BACK      CO_BIT(5)
#define IPC_IRQ_A2E_RXDESC_BACK     CO_BIT(4)
#define IPC_IRQ_A2E_MSG             CO_BIT(1)
#define IPC_IRQ_A2E_DBG             CO_BIT(0)
#define IPC_IRQ_A2E_ALL             (IPC_IRQ_A2E_TXDESC|IPC_IRQ_A2E_MSG|IPC_IRQ_A2E_DBG)



#define IPC_IRQ_E2A_TXCFM_POS   7

#if RW_MUMIMO_TX_EN
#ifdef CFG_IPC_VER_V10
#error "MU-MIMO cannot be compiled for old IPC"
#endif
#if RW_USER_MAX > 3
#define IPC_IRQ_E2A_USER_MSK       0xF
#elif RW_USER_MAX > 2
#define IPC_IRQ_E2A_USER_MSK       0x7
#else
#define IPC_IRQ_E2A_USER_MSK       0x3
#endif

#define IPC_IRQ_E2A_AC0_OFT        7
#define IPC_IRQ_E2A_AC0_MSK       (IPC_IRQ_E2A_USER_MSK << IPC_IRQ_E2A_AC0_OFT)
#define IPC_IRQ_E2A_AC1_OFT       (IPC_IRQ_E2A_AC0_OFT + RW_USER_MAX)
#define IPC_IRQ_E2A_AC1_MSK       (IPC_IRQ_E2A_USER_MSK << IPC_IRQ_E2A_AC1_OFT)
#define IPC_IRQ_E2A_AC2_OFT       (IPC_IRQ_E2A_AC1_OFT + RW_USER_MAX)
#define IPC_IRQ_E2A_AC2_MSK       (IPC_IRQ_E2A_USER_MSK << IPC_IRQ_E2A_AC2_OFT)
#define IPC_IRQ_E2A_AC3_OFT       (IPC_IRQ_E2A_AC2_OFT + RW_USER_MAX)
#define IPC_IRQ_E2A_AC3_MSK       (IPC_IRQ_E2A_USER_MSK << IPC_IRQ_E2A_AC3_OFT)
#define IPC_IRQ_E2A_BCN_OFT       (IPC_IRQ_E2A_AC3_OFT + RW_USER_MAX)
#define IPC_IRQ_E2A_BCN_MSK       CO_BIT(IPC_IRQ_E2A_BCN_OFT)

#define IPC_IRQ_E2A_AC_TXCFM     (IPC_IRQ_E2A_AC0_MSK | IPC_IRQ_E2A_AC1_MSK | \
                                   IPC_IRQ_E2A_AC2_MSK | IPC_IRQ_E2A_AC3_MSK)

#if !NX_BEACONING || (NX_BCN_AUTONOMOUS_TX && !NX_UMAC_PRESENT)
#define IPC_IRQ_E2A_BCN_TXCFM      0
#else
#define IPC_IRQ_E2A_BCN_TXCFM      (0x01 << IPC_IRQ_E2A_BCN_OFT)
#endif

#define IPC_IRQ_E2A_TXCFM          (IPC_IRQ_E2A_AC_TXCFM | IPC_IRQ_E2A_BCN_TXCFM)

#else

#if !NX_BEACONING || (NX_BCN_AUTONOMOUS_TX && !NX_UMAC_PRESENT)
#define IPC_IRQ_E2A_TXCFM          ((1 << 4) - 1 ) << IPC_IRQ_E2A_TXCFM_POS
#else
#define IPC_IRQ_E2A_TXCFM          ((1 << 5) - 1 ) << IPC_IRQ_E2A_TXCFM_POS
#endif

#endif /* RW_MUMIMO_TX_EN */


#define IPC_IRQ_E2A_UNSUP_RX_VEC CO_BIT(7)
#define IPC_IRQ_E2A_RADAR       CO_BIT(6)
#define IPC_IRQ_E2A_TBTT_SEC    CO_BIT(5)
#define IPC_IRQ_E2A_TBTT_PRIM   CO_BIT(4)
#define IPC_IRQ_E2A_RXDESC      CO_BIT(3)
#define IPC_IRQ_E2A_MSG_ACK     CO_BIT(2)
#define IPC_IRQ_E2A_MSG         CO_BIT(1)
#define IPC_IRQ_E2A_DBG         CO_BIT(0)
#define IPC_IRQ_E2A_ALL         ( IPC_IRQ_E2A_TXCFM         \
                                | IPC_IRQ_E2A_RXDESC        \
                                | IPC_IRQ_E2A_MSG_ACK       \
                                | IPC_IRQ_E2A_MSG           \
                                | IPC_IRQ_E2A_DBG           \
                                | IPC_IRQ_E2A_TBTT_PRIM     \
                                | IPC_IRQ_E2A_TBTT_SEC      \
                                | IPC_IRQ_E2A_RADAR         \
                                | IPC_IRQ_E2A_UNSUP_RX_VEC)



#endif // _IPC_SHARED_H_

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